28953-DSH-001-A Datasheet, PDF (1/173 Pages) M/A-COM Technology Solutions, Inc. – HDSL Channel Unit

RS8953B/8953SPB
HDSL Channel Unit
The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed Distinguishing Features
to perform data, clock, and format conversions necessary to construct a Pulse Code _{• Supports All HDSL Bit Rates}
Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel
– 2 pair T1 standard (784 kbps)
consists of transmit and receive data, clock and frame sync signals configured for
– 2 pair E1 standard (1168 kbps)
standard T1 (1544 kbps), standard E1 (2048 kbps), or custom (Nx64 kbps) formats.
– 3 pair E1 standard (784 kbps)
The PCM channel connects directly to a Bt8370 T1/E1 Controller or similar T1/E1 device. ^{– 1/2/3 pair custom (Nx64 kbps,}
Connection to other network/subscriber physical layer devices is supported by the
N=2-36)
custom PCM frame format. Three identical HDSL channel interfaces consist of serial ^{• T1/E1 Primary Rate (PCM) Channel}
data and clock connected to a Bt8970 HDSL Transceiver or similar 2B1Q bit pump
device. The RS8953SPB contains one HDSL channel interface.
– Connects to Conexant E1/T1
Framers
– Framed or unframed mode
Control and status registers are accessed via the Microprocessor Unit (MPU)
– Sync/Async payload mapping
interface. One common register group configures the PCM interface formatter,
– Clock recovery/jitter attenuation
Pseudo-Random Bit Sequence (PRBS) generator, Bit Error Rate (BER) meter, timeslot
– PRBS/fixed test patterns
router, Digital Phase Lock Loop (DPLL) clock recovery, and PCM Loopbacks (LB). Three – BER measurement
groups of HDSL channel registers configure the elastic store FIFOs, overhead MUXes, • HDSL Channels
receive framers, payload mappers, and HDSL loopbacks. Status registers monitor
– Connects to Conexant ZipWire
received overhead, DPLL, FIFO, and framer operations, including CRC and FEBE error
Transceivers
counts.
The RS8953B adheres to Bellcore TA-NWT-001210 and FA-NWT-001211 and the
latest ETSI RTR/TM-03036 standards. C-language software for all standard T1/E1
configuration and startup procedures is implemented on Conexant's HDSL Evaluation
Module (Bt8973EVM) and is available under a no-fee license agreement. RS8953B
software can also be developed for non-standard HDSL applications or to interoperate
– Three independent serial channels
– Central, remote, or repeater
– Overhead (HOH) management
– Programmable path delays
– Error performance monitoring
– Software controlled EOC and IND
– Auxiliary payload/Z-bit data link
with existing HDSL equipment.
– Master loop ID and interchange
– Auto tip/ring reversal
Functional Block Diagram
Drop
Insert
PRBS
LB
Elastic
Store
Mapper
HOH Mux
Stuff
2B1Q
Encoder
LB
HDSL
Channels
1, 2, 3
• Programmable Data Routing
– PCM timeslots – HDSL payload
– Drop/Insert – HDSL payload
– Auxiliary – HDSL payload
– PRBS/Fixed – PCM or HDSL
– PCM and HDSL loopbacks
• Intel^® or Motorola^® MPU interface
PCM
Channel
BER
Elastic
Store
Payload
Mapper
2B1Q
Decoder
• CMOS technology, 3.3 V operation
• 68-pin PLCC or 80-pin PQFP
Applications
• Full, Fractional or Multipoint T1/E1
MPU
Registers
DPLL
Receive
Framer
• Single and Multichannel Repeaters
• Voice Pair Gain Systems
• Wireless LAN/PBX
Microprocessor PLL Filter
• PCS, Cellular Base Station
• Fiber Access/Distribution
• Loop Carrier, Remote Switches
• Subscriber Line Modem
Data Sheet
D8953BDSB
March 30, 1999