LTC3728 Datasheet, PDF (9/32 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

W
FU CTIO AL DIAGRA
LTC3728
PLLIN
F_IN
50k
PLLFLTR
R_LP
C_LP
PGOOD
PHASE DET
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
INTV_CC
V_IN
BOOST
D_B
OSCILLATOR
CLK1
CLK2
0.86V
V_OSENSE1
0.74V
0.86V
V_OSENSE2
DROP
OUT
DET
SQ
RQ
BOT FCB
TOP ON
TG
TOP
SW
SWITCH
LOGIC
INTV_CC
BG
BOT
0.55V
+B
–
SHDN
PGND
C_B
+
D₁
C_IN
C_OUT
+
R_SENSE
V_SEC
1.5V
0.18µA
R6
FCB
4.5V –
+
+
R5
–
0.74V
BINH
FCB
3.3V_OUT
0.8V
V_REF
V_IN
V_IN
EXTV_CC
INTV_CC
+^5V
SGND
4.7V +
–
5V
LDO
REG
INTERNAL
SUPPLY
I1
I2
–
– ++ –
+
0.86V
3mV
4(V_FB)
SLOPE
COMP
45k
45k
2.4V
EA
OV
1.2µA
6V
SHDN
RST
4(V_FB)
RUN
SOFT
START
INTV_CC
30k ^SENSE+
30k ^SENSE–
V_FB
0.80V
V_OSENSE
0.86V
I_TH
RUN/SS
D_SEC
R2
R1
C_C
C_C2
R_C
C_SS
+
C_SEC
V_OUT
3728 FD/F02
Figure 2
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3728 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera-
tion, each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I₁, resets the RS latch. The peak
inductor current at which I₁ resets the RS latch is con-
trolled by the voltage on the I_TH pin, which is the output of
each error amplifier EA. The V_OSENSE pin receives the
voltage feedback signal, which is compared to the internal
reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in V_OSENSE relative to
the 0.8V reference, which in turn causes the I_TH voltage to
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