LTC3728 Datasheet, PDF (8/32 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
PI FU CTIO S G Package/UH Package
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina-
tion of soft-start, run control inputs and short-circuit detec-
tion timers. A capacitor to ground at each of these pins sets
the ramp time to full output current. Forcing either of these
pins back below 1.0V causes the IC to shut down the
circuitry required for that particular controller. Latchoff
overcurrent protection is also invoked via this pin as de-
scribed in the Applications Information section.
SENSE1⁺, SENSE2⁺ (Pins 2, 14/Pins 30, 12): The (+) Input
to the Differential Current Comparators. The I_th pin voltage
and controlled offsets between the SENSE^– and SENSE⁺
pins in conjunction with R_SENSE set the current trip thresh-
old.
SENSE1^–, SENSE2^– (Pins 3, 13/Pins 31, 11): The (–) Input
to the Differential Current Comparators.
V_OSENSE1, V_OSENSE2 (Pins 4, 12/Pins 1, 9): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Low-
pass Filter is Tied to This Pin. Alternatively, this pin can be
driven with an AC or DC voltage source to vary the fre-
quency of the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input. This
input acts on both controllers and is normally used to
regulate a secondary winding. Pulling this pin below 0.8V
will force continuous synchronous operation.
I_TH1, I_TH2 (Pins 8, 11/Pins 5, 8): Error Amplifier Output and
Switching Regulator Compensation Point. Each associated
channels’ current comparator trip point increases with this
control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the
C_OUT capacitors.
3.3V_OUT (Pin 10/Pin 7): Output of a linear regulator capable
of supplying 10mA DC with peak currents as high as 50mA.
NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an-
odes of the Schottky rectifiers and the (–) terminal(s) of C_IN.
INTV_CC (Pin 21/Pin 20): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTV_CC Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
EXTV_CC (Pin 22/Pin 21): External Power Input to an
Internal Switch Connected to INTV_CC. This switch closes
and supplies V_CC power, bypassing the internal low drop-
out regulator, whenever EXTV_CC is higher than 4.7V. See
EXTV_CC connection in Applications section. Do not exceed
7V on this pin.
BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
Drives for Bottom (Synchronous) N-Channel MOSFETs.
Voltage swing at these pins is from ground to INTV_CC.
V_IN (Pin 24/Pin 23): Main Supply Pin. A bypass capacitor
should be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped
Supplies to the Top Side Floating Drivers. Capacitors are
connected between the boost and switch pins and Schot-
tky diodes are tied between the boost and INTV_CC pins.
Voltage swing at the boost pins is from INTV_CC to (V_IN +
INTV_CC).
SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to V_IN.
TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to INTV_CC –
0.5V superimposed on the switch node voltage SW.
PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on either V_OSENSE pin
is not within ±7.5% of its set point.
Exposed Pad (Pin 33) SGND: The exposed pad must be
soldered to PCB ground for elecrical contact and rated
thermal performance.
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