LTC3728 Datasheet, PDF (18/32 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
APPLICATIO S I FOR ATIO
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.
compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:
Topside MOSFET Driver Supply (C_B, D_B)
External bootstrap capacitors C_B connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C_B in the functional diagram is charged though
external diode D_B from INTV_CC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the C_B voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
V_IN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V_BOOST =
V_IN + V_INTVCC. The value of the boost capacitor C_B needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than V_IN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
Output Voltage
The LTC3728 output voltages are each set by an external
feedback resistive divider carefully placed across
the output capacitor. The resultant feedback signal is
V_OUT
=
⎛
0.8V_⎝⎜1+
R2^⎞
R1⎠⎟
where R1 and R2 are defined in Figure 2.
SENSE⁺/SENSE^– Pins
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV_CC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTV_CC. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V_OUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
I_SENSE+ + I_SENSE– = (2.4V – V_OUT)/24k
Since V_OSENSE is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.
OPTIONAL EXTV_CC
CONNECTION
5V < V_SEC < 7V
V_IN
+
C_IN
V_IN
LTC3728
TG1
N-CH
EXTV_CC
SW
T1
1:N
R6
FCB
BG1
R5
SGND
N-CH
PGND
V_SEC
+
R_SENSE
1µF
V_OUT
+
C_OUT
3728 F06a
Figure 6a. Secondary Output Loop & EXTV_CC Connection
18
V_IN
+
C_IN
V_IN
LTC3728
TG1
EXTV_CC
N-CH
SW
BG1
N-CH
PGND
+
1µF
BAT85
0.22µF
BAT85
VN2222LL
R_SENSE
L1
BAT85
V_OUT
+
C_OUT
3728 F06b
Figure 6b. Capacitive Charge Pump for EXTV_CC
3728fb