LTC3728 Datasheet, PDF (23/32 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
APPLICATIO S I FOR ATIO
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V_IN current typically results in a small (<0.1%) loss.
2. INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV_CC to
ground. The resulting dQ/dt is a current out of INTV_CC that
is typically much larger than the control circuit current. In
continuous mode, I_GATECHG =f(Q_T+Q_B), where Q_T and Q_B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV_CC power through the EXTV_CC switch input
from an output-derived source will scale the V_IN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV_CC current results in approxi-
mately 2.5mA of V_IN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V_IN) to only a few percent.
3. I²R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R_SENSE,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R_DS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L,
R_SENSE and ESR to obtain I²R losses. For example, if each
R_DS(ON) = 30mΩ, R_L = 50mΩ, R_SENSE = 10mΩ and R_ESR
= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V_OUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V_IN2 I_O(MAX) C_RSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C_IN has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a mini-
mum of 20µF to 40µF of capacitance having a maximum
of 20mΩ to 50mΩ of ESR. The LTC3728 2-phase architec-
ture typically halves this input capacitance requirement
over competing solutions. Other losses including Schottky
conduction losses during dead-time and inductor core
losses generally account for less than 2% total additional
loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V_OUT shifts by an
amount equal to ∆I_LOAD (ESR), where ESR is the effective
series resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I_TH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
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