LTC3728 Datasheet, PDF (26/32 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3728. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C_IN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined LTC3728 signal ground pin and the ground
return of C_INTVCC must return to the combined C_OUT (–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C_IN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capaci-
tors next to each other and away from the Schottky loop
described above.
3. Do the LTC3728 V_OSENSE pins resistive dividers con-
nect to the (+) terminals of C_OUT? The resistive divider
must be connected between the (+) terminal of C_OUT and
1
RUN/SS1
28
PGOOD
2 _SENSE1+
27
TG1
R2
R1
3 _SENSE1–
4
V_OSENSE1
5
PLLFLTR
f_IN
6
PLLIN
26
SW1
25
BOOST1
24
V_IN
23
BG1
INTV_CC
7
FCB
8
I_TH1
22
EXTV_CC
LTC3728
21
INTV_CC
9
SGND
20
PGND
10
3.3V
3.3V_OUT
19
BG2
11
I_TH2
18
BOOST2
R3
R4
12
V_OSENSE2
13 _SENSE2–
17
SW2
16
TG2
14 _SENSE2+
15
RUN/SS2
R_PU
V_PULL-UP
(<7V)
PGOOD
L1
R_SENSE
C_B1
M1
M2
D1
V_OUT1
C_OUT1
R_IN
C_IN
C_VIN
V_IN
C_INTVCC
C_OUT2
D2
C_B2
M3
M4
R_SENSE
L2
GND
V_OUT2
3728 F10
Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram
3728fb
26