LTC3541-1 Datasheet, PDF (9/20 Pages) Linear Technology – High Efficiency Buck + VLDO Regulator

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OPERATIO
buck regulator without the need for external pin control.
A detailed discussion of the transitions between the VLDO
and linear regulator can be found in the VLDO/Linear
Regulator Loop section.
Buck Regulator Control Loop
The LTC3541-1 internal buck regulator uses a constant
frequency, current mode, step-down architecture. Both the
main (top, P-channel MOSFET) and synchronous (bottom,
N-channel MOSFET) switches are internal. During normal
operation, the internal main switch is turned on at the be-
ginning of each clock cycle provided the internal feedback
voltage to the buck is less than the reference voltage. The
current into the inductor provided to the load increases
until the current limit is reached. Once the current limit is
reached the main switch turns off and the energy stored
in the inductor flows through the bottom synchronous
switch into the load until the next clock cycle.
The peak inductor current is determined by comparing the
buck feedback signal to an internal 0.8V reference. When
the load current increases, the output of the buck and
hence the buck feedback signal decrease. This decrease
causes the peak inductor current to increase until the aver-
age inductor current matches the load current. While the
main switch is off, the synchronous switch is turned on
until either the inductor current starts to reverse direction
or the beginning of a new clock cycle.
When the MODE pin is driven to a logic low, the LTC3541‑1
buck regulator operates in Burst Mode operation for high
efficiency. In this mode, the main switch operates based
upon load demand. In Burst Mode operation the peak
inductor current is set to a fixed value, where each burst
event can last from a few clock cycles at light loads to
nearly continuous cycling at moderate loads. Between
burst events the main switch and any unneeded circuitry
are turned off, reducing the quiescent current. In this sleep
state, the load is being supplied solely from the output
capacitor. As the output voltage droops, an internal error
amplifier’s output rises until a wake threshold is reached
causing the main switch to again turn on. This process
repeats at a rate that is dependant upon the load current
demand.
LTC3541-1
When the MODE pin is driven to a logic high the LTC3541-1
operates in Pulse-Skip mode for low output voltage ripple.
In this mode, the LTC3541-1 continues to switch at a
constant frequency down to very low currents, where it
will begin skipping pulses used to control the main (top)
switch to maintain the proper average inductor current.
If the input supply voltage is decreased to a value ap-
proaching the output voltage, the duty cycle of the buck
is increased toward maximum on-time and 100% duty
cycle. The output voltage will then be determined by the
input voltage minus the voltage drop across the main
switch and the inductor.
VLDO/Linear Regulator Loop
In the LTC3541-1, the VLDO and linear regulator loops
consist of an amplifier and N-channel MOSFET output
stages that, when connected with the proper external
components, will servo the output to maintain a regula-
tor output voltage, LV_OUT. The internal reference voltage
provided to the amplifier is 0.4V allowing for a wide range
of output voltages. Loop configurations enabling the VLDO
or the linear regulator are stable with an output capacitance
as low as 2.2µF and as high as 100µF. Both the VLDO
and the linear regulators are capable of operating with an
input voltage, V_IN, as low as 2.7V, but are subject to the
constraint that V_IN must be greater than LV_OUT + 1.4V.
The VLDO is designed to provide up to 300mA of output
current at a very low LV_IN to LV_OUT voltage. This allows
a clean, secondary, analog supply voltage to be provided
with a minimum drop in efficiency. The VLDO is provided
with thermal protection that is designed to disable the
VLDO function when the output, pass transistor’s junction
temperature reaches approximately 160°C. In addition to
thermal protection, short-circuit detection is provided to
disable the VLDO function when a short-circuit condition
is sensed. This circuit is designed such that an output
current of approximately 1A can be provided before this
circuit will trigger. As detailed in the Electrical Character-
istics, the VLDO regulator will be out of regulation when
this event occurs. Both the thermal and short-circuit faults
when detected are treated as catastrophic fault condi-
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