LTC3541-1 Datasheet, PDF (13/20 Pages) Linear Technology – High Efficiency Buck + VLDO Regulator

LTC3541-1
APPLICATIO S I FOR ATIO
resistance of C_OUT. ΔI_LOAD also begins to charge or dis-
charge C_OUT, which generates a feedback error signal. The
regulator loop then acts to return V_OUT to its steady-state
value. During this recovery time V_OUT can be monitored
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C_OUT, causing a rapid drop in V_OUT. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 • C_LOAD). Thus, a 10µF capacitor charging to 3.3V
would require a 250µs rise time, limiting the charging
current to about 130mA.
VLDO/Linear regulator
Adjustable Output Voltage
The LTC3541-1 LV_OUT output voltage is set by the ratio of
two external resistors as shown in Figure 7. The device
servos LV_OUT to maintain the LFB pin voltage at 0.4V
(referenced to ground). Thus, the current in R1 is equal
to 0.4V/R1. For good transient response, stability, and ac-
curacy, the current in R1 should be at least 2µA, thus the
value of R1 should be no greater than 200k. The current
in R2 is the current in R1 plus the LFB pin bias current.
Since the LFB pin bias current is typically <10nA, it can be
ignored in the output voltage calculation. The output volt-
age can be calculated using the formula in Figure 8. Note
that in shutdown the output is turned off and the divider
current will be zero once C_OUT is discharged.
The LTC3541-1 VLDO and linear regulator loops operate
at a relatively high gain of –3.5µV/mA and –3.4µV/mA
respectively, referred to the LFB input. Thus, a load cur-
rent change of 1mA to 300mA produces a 1.05mV drop
at the LFB input for the VLDO and a load current change
of 1mA to 30mA produces a 0.1mV drop at the LFB input
LV_OUT
LTc3541-1
LFB
GND
( ) ^{VOUT = 0.4V}
1+
R2
R1
R2
c_OUT
R1
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Figure 7. Programming the LTC3541-1
for the linear regulator. To calculate the change referred
to the output simply multiply by the gain of the feedback
network (i.e., 1 + R2/R1). For example, to program the
output for 1.2V choose R2/R1 = 2. In this example, an
output current change of 1mA to 300mA produces 1.05mV
• (1 + 2) = 3.15mV drop at the output.
Since the LFB pin is relatively high impedance (depending
on the resistor divider used), stray capacitance at this pin
should be minimized (<10pF) to prevent phase shift in the
error amplifier loop. Additionally, special attention should
be given to any stray capacitances that can couple external
signals onto the LFB pin producing undesirable output
ripple. For optimum performance connect the LFB pin to
R1 and R2 with a short PCB trace and minimize all other
stray capacitance to the LFB pin.
Output Capacitance and Transient Response
The LTC3541-1 is designed to be stable with a wide range
of ceramic output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small capacitors. A
minimum output capacitor of 2.2µF with an ESR of 0.05Ω
or less is recommended to ensure stability. The LTC3541-1
VLDO is a micropower device and output transient response
will be a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
provide improved transient response for larger load current
changes. Note that bypass capacitors used to decouple
individual components powered by the LTC3541-1 will
increase the effective output capacitor value. High ESR
tantalum and electrolytic capacitors may be used, but
a low ESR ceramic capacitor must be in parallel at the
output. There is no minimum ESR or maximum capacitor
size requirement.
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