LTC3541-1 Datasheet, PDF (15/20 Pages) Linear Technology – High Efficiency Buck + VLDO Regulator

LTC3541-1
APPLICATIO S I FOR ATIO
proportional to frequency. Both the DC bias and gate charge
losses are proportional to V_IN and thus their effects will
be more pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R_DS(ON) and the duty cycle (DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
3. Losses in the VLDO/linear regulator are due to the DC bias
currents as given in the Electrical Characteristics and to the
(V_IN – V_OUT) voltage drop across the internal output device
transistor.
Other losses when the buck and VLDO are in operation
(ENBUCK and ENVLDO equal logic high), including C_IN
and C_OUT ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
THERMAL CONSIDERATIONS
The LTC3541-1 requires the package backplane metal
(GND pin) to be well soldered to the PC board. This gives
the DFN package exceptional thermal properties. The
power handling capability of the device will be limited
by the maximum rated junction temperature of 125°C.
The LTC3541-1 has internal thermal limiting designed to
protect the device during momentary overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat-spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat gener-
ated by power devices.
To avoid the LTC3541-1 exceeding the maximum junction
temperature, some thermal analysis is required. The goal
of the thermal analysis is to determine whether the power
dissipated exceeds the maximum junction temperature of
the part. The temperature rise is given by:
T_R = P_D • q_JA
where P_D is the power dissipated by the regulator and q_JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3541-1 with an input
voltage V_IN of 2.9V, an LV_IN voltage of 1.8V, an LV_OUT
voltage of 1.5V, a load current of 200mA for the buck,
a load current of 300mA for the VLDO and an ambient
temperature of 85°C. From the typical performance graph
of switch resistance, the R_DS(ON) of the P-channel switch
at 85°C is approximately 0.25Ω. The R_DS(ON) of the N-
channel switch is approximately 0.4Ω. Therefore, power
dissipated by the part is approximately:
P_D = (I_LOADBUCK)² • R_SW + (I_LOADVLDO) •
(LV_IN – LV_OUT) = 167mW
For the 3mm × 3mm DFN package, the q_JA is 43°C/W.
Thus, the junction temperature of the regulator is:
T_J = 85°C + (0.167)(43) = 92°C
which is well below the maximum junction temperature
of 125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R_DS(ON).
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