LTC3541-1 Datasheet, PDF (14/20 Pages) Linear Technology – High Efficiency Buck + VLDO Regulator

LTC3541-1
APPLICATIO S I FOR ATIO
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U
and Y5V dielectrics are good for providing high capaci-
tances in a small package, but exhibit large voltage and
temperature coefficients as shown in Figures 8 and 9.
When used with a 2V regulator, a 1µF Y5V capacitor can
lose as much as 75% of its initial capacitance over the
operating temperature range. The X5R and X7R dielectrics
result in more stable characteristics and are usually more
suitable for use as the output capacitor. The X7R type has
better stability across temperature, while the X5R is less
20
BOTH cAPAcITORS ARE 1µF,
10V, 0603 cASE SIZE
0
X5R
–20
–40
Y5V
–60
–80
–100
0
2
4
6
8
10
Dc BIAS VOLTAGE (V)
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Figure 8. Change in Capacitor vs Bias Voltage
20
0
X5R
–20
Y5V
–40
–60
–80
BOTH cAPAcITORS ARE 1µF,
10V, 0603 cASE SIZE
–100
–50 –25 0
25 50 75
TEMPERATURE (°c)
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Figure 9. Change in Capacitor vs Temperature
expensive and is available in higher values. In all cases,
the output capacitance should never drop below 1µF or
instability or degraded performance may occur.
EFFICIENCY CONSIDERATIONS
Generally, the efficiency of a regulator is equal to the out-
put power divided by the input power times 100%. It is
often useful to analyze individual loss terms to determine
which terms are limiting efficiency and what if any change
would yield the greatest improvement. Efficiency can be
expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual loss terms as a per-
centage of input power.
Although all dissipative elements in the circuit produce
losses, three main sources typically account for the majority
of the losses in the LTC3541-1 circuits: V_IN quiescent cur-
rent, I²R losses and loss across VLDO output device. When
operating with both the buck and VLDO active (ENBUCK
and ENVLDO equal to logic high), V_IN quiescent current
loss and loss across the VLDO output device dominate
the efficiency loss at low load currents, whereas the I²R
loss and loss across the VLDO output device dominate
the efficiency loss at medium to high load currents. At
low load currents with the part operating with the linear
regulator (ENBUCK equal to logic low, ENVLDO equal to
logic high), efficiency is typically dominated by the loss
across the linear regulator output device and V_IN quiescent
current. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of little consequence.
1. The V_IN quiescent current loss in the buck is due to two
components: the DC bias current as given in the Electrical
Characteristics and the internal main switch and synchro-
nous switch gate charge currents. The gate charge current
results from switching the gate capacitance of the internal
power switches. Each time the gate is switched from high
to low to high again, a packet of charge, dQ, moves from
V_IN to ground. The resulting dQ/dt is the current out of
V_IN that is typically larger than the DC bias current and
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