LTC3114-1_15 Datasheet, PDF(9/34 Page) Linear Technology – 40V, 1A Synchronous Buck-Boost DC/DC Converter with Programmable Output Current

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LTC3114-1_15 Datasheet, PDF (9/34 Pages) Linear Technology – 40V, 1A Synchronous Buck-Boost DC/DC Converter with Programmable Output Current

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LTC3114-1

PIN FUNCTIONS

PGND (Pin 1, Exposed Pad Pin 17): Power Ground Con-

nections. The PGND pin must be electrically connected

to a power ground plane in the application. The exposed

pad is an additional power ground connection in parallel

with Pin 1. Optimal thermal performance requires that the

exposed pad be soldered to the PC board and preferably

to a ground plane.

SW2 (Pin 2): Buck-Boost Converter Power Switch Pin. This

pin is connected to one side of the buck-boost inductor.

PVOUT (Pin 3): Buck-Boost Converter Power Output. This

pin should be connected to a low ESR capacitor of at least

10ÂµF. The capacitor should be placed as close to the IC as

possible and should have a short return path to PGND.

RUN (Pin 4): Input to Enable and Disable the IC and Set

Custom Input Undervoltage Lockout (UVLO) Thresholds.

The RUN pin can be driven by an external logic signal to

enable and disable the IC. In addition, the voltage on this

pin can be set by a resistive voltage divider connected

to the input voltage in order to provide accurate turn-on

and turn-off (UVLO) thresholds. The IC is enabled if RUN

exceeds 1.2V nominally. Once enabled, the UVLO threshold

has built-in hysteresis of approximately 100mV, so turn-

off will occur when the voltage on RUN drops to below

1.1V nominally. To continuously enable the IC, RUN can

be tied directly to the input voltage up to the absolute

maximum rating.

PROG (Pin 5): Output Current Programming Pin and

Output of the Switch D Current Sense Amplifier. A current

proportional to the current in switch D, the buck-boost

converter output current, is delivered from PROG. The

PROG current magnitude is approximately ISWD/25000.

Connect a parallel resistor and capacitor from PROG to

GND to generate a voltage proportional to output current.

In applications where this voltage is used to control aver-

age output current, the resistor value should be set such

that the desired average output current produces 1V on

PROG and is given by:

RPROG(â¦)

1Vâ¢ 25000

IOUT (A)

Alternatively, the voltage on PROG can be connected

to an A/D converter and used for system diagnostic

functions. Refer to the Applications Information section

for complete details on how to select the proper values

for RPROG and CPROG.

VC (Pin 6): Error Amplifier Output. A frequency compensa-

tion network must be connected between VC and GND to

stabilize the buck-boost converter. Refer to the Applications

Information section for details.

FB (Pin 7): Feedback Voltage Input. A resistor divider

connected to this pin sets the output voltage for the

buck-boost converter. The nominal FB voltage is 1V. Care

should be taken in the routing of the connection to this

pin to minimize the possibility of stray coupling from the

SW pins.

GND (Pin 8): Signal Ground. This pin is the ground con-

nection for the control circuitry of the IC and must be tied

to ground in the application.

LDO (Pin 9): Low Voltage Supply Input for the IC Control

Circuitry. This pin powers internal IC control circuitry

and must be connected to the LDO pin in the application.

A 4.7ÂµF or larger bypass capacitor must be connected

between this pin and ground. Pins LDO and PLDO must

be connected together in the application.

VIN (Pin 10): LDO Supply Connection. This pin provides

power to the internal VCC regulator. Pins VIN and PVIN

must be connected together in the application. If the

trace connecting VIN and PVIN is of substantial length, a

1ÂµF capacitor should be connected from VIN to GND as

close to the IC pins as possible.

PLDO (Pin 11): Internal LDO Regulator Output. PLDO is

the output of the internal linear regulator that generates

the LDO rail from VIN. PLDO is also used as the supply

connection to the power switch gate drivers. Pins PLDO

and LDO must be connected together in the application.

BST2 (Pin 12): Flying Capacitor Pin for SW2. This pin must

be connected to SW2 through a 68nF capacitor. BST2 is

used to generate the gate driver rail for power switch D.

BST1 (Pin 13): Flying Capacitor Pin for SW1. This pin must

be connected to SW1 through a 68nF capacitor. BST1 is

used to generate the gate driver rail for power switch A.

For more information www.linear.com/LTC3114-1

31141fa

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