LTC3114-1_15 Datasheet, PDF (25/34 Pages) Linear Technology – 40V, 1A Synchronous Buck-Boost DC/DC Converter with Programmable Output Current

LTC3114-1
APPLICATIONS INFORMATION
be selected based on the guidelines provided elsewhere
in this data sheet. Particular attention needs to be paid
to the voltage bias effect on ceramic capacitors typically
used for output bypassing. Similarly, it is assumed that
the inductor value and current rating has been selected
as well based on the application requirements.
Example Application Details:
V_IN = 9V to 36V
V_OUT = 12V
Maximum I_OUT (boost mode) = 700mA, R_LOAD (min)
= 12V/0.7A = 17.1Ω
Maximum I_OUT (buck mode) = 1A, R_LOAD (min) = 12Ω
C_OUT = 44µF
L = 10µH
Since this application includes boost mode operation, the
first step is to calculate the worst-case RHPZ frequency
as this will dictate the maximum loop bandwidth for the
converter:
RHPZ(f) = ^{VIN2 •RLOAD} (Hz)
V_OUT2 • 2π •L
substituting the values mentioned earlier yields:
RHPZ(f)
=
9V
12V²
2
•
• 17.1Ω
2π •10µH
=
153.1kHz
In order to account for internal IC component variations, it
is good practice to set the converter bandwidth or cross-
over frequency at least three times lower than the RHPZ
frequency to avoid excessive phase loss from the RHPZ
when operating in boost mode. In some instances such
as higher output voltage applications, an even greater
separation between the loop crossover frequency and the
RHPZ frequency may be necessary. In this example design,
we’ll plan to achieve a loop bandwidth (f_CC) of 29kHz or
approximately one-fifth the RHPZ frequency.
The system poles and zeros are as follows:
Output Load Pole (P1)
=
1
;
2π •R_LOAD •C_OUT
buck mode, where R_LOAD = output resistance.
In boost mode this equation is slightly different:
( ) ²
,
2π •R_LOAD •C_OUT ′
but with the reduced output current capability in boost
(higher R_LOAD), the load pole location is about the same.
Error Amp Pole
(P2)
=
1
(^{2π •R}_EA
•C_{C )}^;
this pole is very close to DC, R_EA = error amp output
resistance, which is approximately 3.6MΩ. It has no
impact on the compensation design, but is included
here for completeness.
Compensation Zero (Z1)
=
(2π
1
•R_Z
•
C_P1)
;
R_Z and C_P1 are the error amp compensation components
that will be selected.
Ignoring very high frequency output capacitor ESR zero
and secondary high frequency error amp pole, the system
has two poles and one zero. The error amp pole (P2) is
always near DC and we have little influence on it. The
output load pole (P1) will move depending on buck-boost
converter load resistance. The highest frequency for P1, the
output load pole, is at maximum load current (minimum
R_LOAD). If we design the error amp zero (Z1) frequency
so that it coincides with P1(max), then we will get the
maximum phase benefit from the compensation network
at full load and enough phase boost at lighter loads for
stable operation and a single pole response where the
loop crosses zero dB.
Assuming the error amp zero is designed as just described,
at frequencies above P2 (and Z1), the closed-loop gain of
our system simplifies to:
G_CL
=
G_CS
•R_LOAD • g_m
V_OUT
•R_Z
For more information www.linear.com/LTC3114-1
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