LTC3114-1_15 Datasheet, PDF (15/34 Pages) Linear Technology – 40V, 1A Synchronous Buck-Boost DC/DC Converter with Programmable Output Current

LTC3114-1
OPERATION
Burst Mode Operation
When the MODE pin is held low, the LTC3114-1 is config-
ured for Burst Mode operation. As a result, the buck-boost
DC/DC converter will operate with normal continuous PWM
switching above a predetermined minimum output load
and will automatically transition to power saving Burst
Mode operation below this output load level. Refer to the
Typical Performance Characteristics section of this data
sheet to determine the Burst Mode transition threshold
for various combinations of V_IN and V_OUT. If MODE is
low, at light output loads, the LTC3114-1 will go into a
standby or sleep state when the output voltage achieves
its nominal regulation level. The sleep state halts PWM
switching and powers down all non-essential functions
of the IC, significantly reducing the quiescent current
of the LTC3114-1. This greatly improves overall power
conversion efficiency when the output load is light. Since
the converter is not operating in sleep, the output volt-
age will slowly decay at a rate determined by the output
load resistance and the output capacitor value. When the
output voltage has decayed by a small amount, typically
1%, the LTC3114-1 will wake and resume normal PWM
switching operation until the voltage on V_OUT is restored to
the previous level. If the load is very light, the LTC3114‑1
may only need to switch for a few cycles to restore V_OUT
and may sleep for extended periods of time, significantly
improving efficiency.
Soft-Start
The LTC3114-1 soft-start circuit minimizes input current
transients and output voltage overshoot on initial power up.
The required timing components for soft-start are internal
to the LTC3114-1 and produce a nominal soft-start dura-
tion of approximately 2ms. The internal soft-start circuit
slowly ramps the error amplifier output, VC. In doing so,
the current command of the IC is also slowly increased,
starting from zero. It is unaffected by output loading or
output capacitor value. Soft-start is reset by undervolt-
age lockout on both V_IN and LDO, the accurate RUN pin
comparator, thermal shutdown and the overload current
limit as described previously.
LDO REGULATOR
An internal low dropout regulator generates a nominal
4.4V rail from V_IN. The LDO rail powers the internal control
circuitry and power device gate drivers of the LTC3114‑1.
The LDO regulator is disabled in shutdown to reduce
quiescent current and is enabled by forcing the RUN pin
above its logic threshold. The LDO regulator includes
current-limit protection to safeguard against accidental
short-circuiting of the LDO rail. In 5V V_OUT applications,
the LDO can be driven by V_OUT through a Schottky diode,
commonly referred to as bootstrapping. Bootstrapping can
provide a significant efficiency improvement, particularly
when V_IN is very high and also allows operation to the
minimum rated input voltage of 2.2V.
UNDERVOLTAGE LOCKOUT
The LTC3114-1 undervoltage lockout (UVLO) circuit dis-
ables operation of the internal power switches and keeps
other IC functions in a reset state if either the input voltage
applied to V_IN or the LDO output voltage are below their
respective UVLO thresholds. There are two UVLO circuits,
one that monitors V_IN and another that monitors LDO. The
V_IN UVLO comparator has a falling voltage threshold of
2.1V (typical). If V_IN falls below this level, IC operation is
disabled until V_IN rises above 2.2V (typical), as long as
the LDO voltage is above its UVLO threshold. The LDO
UVLO has a falling voltage threshold of 2.4V (typical). If
the LDO voltage falls below this threshold, IC operation
is disabled until LDO rises above 2.5V (typical) as long as
V_IN is above its nominal UVLO threshold level.
Depending on the particular application, either of these
UVLO thresholds could be the limiting factor affecting
the minimum input voltage required for operation. The
LTC3114-1 LDO regulator uses V_IN for its power input. If
LDO is not bootstrapped, then there exists a voltage drop or
dropout voltage between V_IN and LDO. The dropout voltage
is proportional to the loading on LDO, which is primarily
due to the gate charge and capacitive charging currents
inherent to the internal power switches. The loading on LDO
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