LT1010_06 Datasheet, PDF (9/20 Pages) Linear Technology – Fast ±150mA Power Buffer

LT1010
APPLICATIO S I FOR ATIO
be unrealistic to use these worst-case numbers above
because paralleled units are operating under identical
conditions. The offset voltage specified for V_S = ±15V,
V_IN = 0V and T_A = 25°C will suffice for a worst-case
condition.
V⁺
I_S
A1
V_IN
LT1010
I_S
V_OUT
A2
LT1010
∆I_OUT
I_S – ∆I_OUT
I_S + ∆I_OUT
1010 AI03
V^–
Output load current will be divided based on the output
resistance of the individual buffers. Therefore, the avail-
able output current will not quite be doubled unless output
resistances are matched. As for offset voltage, the 25°C
limits should be used for worst-case calculations.
Parallel operation is not thermally unstable. Should one
unit get hotter than its mates, its share of the output and
its standby dissipation will decrease.
As a practical matter, parallel connection needs only some
increased attention to heat sinking. In some applications,
a few ohms equalization resistance in each output may be
wise. Only the most demanding applications should re-
quire matching, and then just of output resistance at 25°C.
Isolating Capacitive Loads
The inverting amplifier below shows the recommended
method of isolating capacitive loads. Noninverting ampli-
fiers are handled similarly.
R_F
R_S
20k
V_IN
–
A1
LT1007
+
C_F
100pF
A2
LT1010
V_OUT
C_L
1010 AI04
At lower frequencies, the buffer is within the feedback loop
so that its offset voltage and gain errors are negligible. At
higher frequencies, feedback is through C_F, so that phase
shift from the load capacitance acting against the buffer
output resistance does not cause loop instability.
Stability depends upon the R_FC_F time constant or the
closed-loop bandwidth. With an 80kHz bandwidth, ring-
ing is negligible for C_L = 0.068µF and damps rapidly for
C_L = 0.33µF. The pulse response is shown in the graph.
Pulse Response
C_L = 0.068µF
5
0
–5
C_L = 0.33µF
5
0
–5
0
50
100
150
200
TIME (µs)
1010 AI05
Small-signal bandwidth is reduced by C_F, but consider-
able isolation can be obtained without reducing it below
the power bandwidth. Often, a bandwidth reduction is
desirable to filter high frequency noise or unwanted
signals.
R_F
2k
R_S
2k
V_IN
–
A1
LT118A
+
C_F
1nF
A2
LT1010
V_OUT
C_L
1010 AI06
The follower configuration is unique in that capacitive
load isolation is obtained without a reduction in small-
signal bandwidth, although the output impedance of the
buffer comes into play at high frequencies. The precision
unity-gain buffer above has a 10MHz bandwidth without
capacitive loading, yet it is stable for all load capacitance
to over 0.3µF, again determined by R_FC_F.
1010fc
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