LT1010_06 Datasheet, PDF (7/20 Pages) Linear Technology – Fast ±150mA Power Buffer

LT1010
APPLICATIO S I FOR ATIO
General
These notes briefly describe the LT1010 and how it is
used; a detailed explanation is given elsewhere¹. Empha-
sis here will be on practical suggestions that have resulted
from working extensively with the part over a wide range
of conditions. A number of applications are also outlined
that demonstrate the usefulness of the buffer beyond that
of driving a heavy load.
Design Concept
The schematic below describes the basic elements of the
buffer design. The op amp drives the output sink transis-
tor, Q3, such that the collector current of the output
follower, Q2, never drops below the quiescent value (de-
termined by I₁ and the area ratio of D1 and D2). As a result,
the high frequency response is essentially that of a simple
follower even when Q3 is supplying the load current. The
internal feedback loop is isolated from the effects of
capacitive loading by a small resistor in the output lead.
D1
A1
I₁
D2
Q2
V⁺
BIAS
I₂
Q1
R1
INPUT
OUTPUT
Q3
V^–
1010 AI01
The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This can
be mitigated by connecting a resistor between the bias
terminal and V ⁺, raising quiescent current. A feature of the
final design is that the output resistance is largely indepen-
dent of the follower quiescent current or the output load
current. The output will also swing to the negative rail,
which is particularly useful with single supply operation.
Equivalent Circuit
Below 1MHz, the LT1010 is quite accurately represented
by the equivalent circuit shown here for both small- and
large-signal operation. The internal element, A1, is an
idealized buffer with the unloaded gain specified for the
LT1010. Otherwise, it has zero offset voltage, bias current
and output resistance. Its output also saturates to the
internal supply terminals².
V⁺
I_B
V_OS
INPUT
+
V_SOS+
R′
R_OUT
A1
OUTPUT
R′ R′ = R_SAT – R_OUT
V_SOS–
V^–
1010 AI02
Loaded voltage gain can be determined from the unloaded
gain, A_V, the output resistance, R_OUT, and the load resis-
tance, R_L, using:
A_VL
=
A_VR_L
R_OUT + R_L
Maximum positive output swing is given by:
V_OUT⁺
=
(V⁺ – V_SOS⁺ )R_L
R_SAT + R_L
The input swing required for this output is:
V_IN⁺
=
V_OUT⁺
⎛
⎝⎜
1+
R_OUT
R_L
⎞
⎠⎟
–
V_OS
+
∆V_OS
where ∆V_OS is the 100mV clipping specified for the
saturation measurements. Negative output swing and
input drive requirements are similarly determined.
Supply Bypass
The buffer is no more sensitive to supply bypassing than
slower op amps as far as stability is concerned. The 0.1µF
disc ceramic capacitors usually recommended for op
amps are certainly adequate for low frequency work. As
always, keeping the capacitor leads short and using a
1_{R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,”}
Linear Technology Corp. TP-1, April, 1984.
2_{See electrical characteristics section for guaranteed limits.}
1010fc
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