LTC3617_15 Datasheet, PDF (7/20 Pages) Linear Technology – 6A Monolithic Synchronous Step-Down Regulator for DDR Termination

LTC3617
Pin Functions
RT (Pin 1): Oscillator Frequency. This pin provides two
ways of setting the constant switching frequency:
1. Connecting a resistor from RT to ground will set the
switching frequency based on the resistor value.
2. Tying the RT pin to SV_IN enables the internal 2.25MHz
oscillator frequency.
SGND (Pin 2): Signal Ground. All small-signal and com-
pensation components should connect to this ground,
which in turn should connect to PGND at a single point.
VTTR (Pin 3): Voltage Buffer Output. This pin is the output
of an internal voltage buffer whose voltage is equal to
VDDQIN • 0.5. Output current capability is ±10mA. VTTR
is also the reference voltage of the error amplifier, which
sets the output voltage. V_FB will regulate to VTTR. Do not
exceed 0.1µF capacitance on this pin.
PV_IN (Pins 4, 10, 11, 17): Power Input Supply. PV_IN con-
nects to the source of the internal P-channel power MOSFET.
This pin is independent of SV_IN and may be connected to
the same supply or to a lower voltage.
SW (Pins 5, 6, 7, 8, 13, 14, 15, 16): Switch Node. Con-
nection to the inductor. These pins connect to the drains
of the internal power MOSFET switches.
NC (Pins 9, 12): Can be connected to ground or left open.
SV_IN (Pin 18): Signal Input Supply. This pin powers the
internal control circuitry and is monitored by the under-
voltage lockout comparator.
RUN (Pin 19): Enable Input. Pulling this pin high enables
the LTC3617 and forcing it to ground shuts the regulator
down. In shutdown, all functions are disabled and the chip
draws <1µA of supply current.
SYNC (Pin 20): External Synchronization Input. When
a clock signal is applied to this pin, the switching fre-
quency synchronizes to this clock signal. This pin can
be either floating or tied to ground if an external clock
is not being used.
PGOOD (Pin 21): Power Good. This open-drain output
is pulled down to SGND on start-up and when the FB
voltage is outside the power good voltage window. If the
FB voltage increases and stays inside the power good
window for more than 100µs the PGOOD pin is released.
If the FB voltage leaves the power good window for more
than 100µs the PGOOD pin is pulled low.
The power good window moves in relation to the VDDQIN
pin voltage. In shutdown the PGOOD output will actively
pull low and may be used to discharge the output capaci-
tors via an external resistor.
V_FB (Pin 22): Voltage Feedback Input Pin. Senses the
feedback voltage from the external resistive divider across
the output.
ITH (Pin 23): Error Amplifier Compensation. The current
comparator’s threshold increases with this control voltage.
Tying this pin to SV_IN enables internal compensation.
VDDQIN (Pin 24): External Reference Input. An internal
resistor divider sets the VTTR and V_FB regulated voltages
to be equal to half the voltage applied to this input.
PGND (Exposed Pad Pin 25): Power Ground. This pin
connects to the source of the internal N-channel power
MOSFET. This pin should be connected close to the (–)
terminal of C_IN and C_OUT.
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