LTC3617_15 Datasheet, PDF (16/20 Pages) Linear Technology – 6A Monolithic Synchronous Step-Down Regulator for DDR Termination

LTC3617
Applications Information
Remembering that the above junction temperature is
obtained from the R_DS(ON) at 25°C, we might recalculate
the junction temperature based on a higher R_DS(ON) since
it increases with temperature. Redoing the calculation
assuming that R_SW increased 15% at 73°C yields a new
junction temperature of 79°C. Therefore, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Note that for very low input voltage, the junction tempera-
ture will be higher due to increased switch resistance,
R_DS(ON). It is not recommended to use full load current
with high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3617 the
exposed pad must be soldered to a ground plane. See the
PCB Layout Board Checklist.
Design Example
As a design example, consider the LTC3617 in an applica-
tion with the following specifications:
V_IN = 2.5V, V_OUT = 1.25V, I_OUT(MAX) = 6A, I_OUT(MIN) =
200mA, f = 2.6MHz.
First, calculate the timing resistor:
R_T
=
3.82¹¹Hz
2.6MHz
–
16k
=
130kΩ
Next, calculate the inductor value for about 33% ripple
current at maximum V_IN:
L
=


1.25V
2.6MHz •
2A


•


1–
1.25V 
2.5V 
=
0.12µH
Using a standard value of 0.1µH inductor results in a
maximum ripple current of:
∆I_L
=


1.25V 
2.6MHz • 0.1µH
•


1–
1.25V
2.5V


=
2.4A
C_IN should be selected for a maximum current rating of:
I_RMS
=
6A
•
1.25V
2.5V
•


2.5V
1.25V
–
1^{}
=
3A_RMS
Decoupling PV_IN with four 10µF to 22µF capacitors is
adequate for most applications. Connecting the V_FB pin
directly to V_OUT will set the output voltage equal to one-half
of the voltage on the VDDQIN pin. The complete circuit of
this design example is illustrated in Figure 1.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3617:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3617.
2. Connect the (+) terminal of the input capacitor(s), C_IN,
as close as possible to the PV_IN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the V_FB pin directly to V_OUT.
C_OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 100µF ceramic capacitor is used with a X5R or X7R
dielectric.
3617fa
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