LTC3617_15 Datasheet, PDF (15/20 Pages) Linear Technology – 6A Monolithic Synchronous Step-Down Regulator for DDR Termination

LTC3617
Applications Information
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V_IN quiescent current and I²R losses. The V_IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I²R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V_IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V_IN to ground. The resulting dQ/dt is the current
into V_IN due to gate charge, and it is typically larger than
the DC bias current. Both the DC bias and gate charge
losses are proportional to V_IN; thus, their effects will
be more pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW , and external inductor, R_L. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3617 does not generate much
heat due to its high efficiency.
However, in high current applications where the LTC3617
is running at high ambient temperature with low supply
voltage and high duty cycles, such as in dropout, the heat
generated may exceed the maximum junction temperature
of the part. If the junction temperature reaches approxi-
mately 160°C, both power switches will be turned off and
the SW node will become high impedance.
To prevent the LTC3617 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
T_RISE = (P_D) • (θ_JA)
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to
the ambient temperature. The junction temperature, T_J,
is given by:
T_J = T_A + T_RISE
where T_A is the ambient temperature.
As an example, consider the case when the LTC3617 is
used in a DDR application where V_IN = 3.3V, I_OUT = 6A,
f = 1MHz, V_OUT = 1.25V. The equivalent power MOSFET
resistance R_SW is:
R_SW
= R_DS(ON)TOP •
V_OUT
V_IN
+
R_DS(ON)BOT
•


1–
V_OUT
V_IN


=
35mΩ
•
1.25
3.3
+
25mΩ
•


1–
1.25 
3.3 
=
28.79mΩ
The V_IN current during 1MHz with no load is about 22mA,
which includes switching and internal biasing current
loss, transition loss, inductor core loss and other losses
in the application. Therefore, the total power dissipated
by the part is:
P_D = I_OUT² • R_SW + V_IN • I_VIN (No Load)
= 36A² • 28.79mΩ + 3.3V • 22mA = 1.11W
The QFN 3mm × 5mm package junction-to-ambient thermal
resistance, θ_JA, is around 43°C/W. Therefore, the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
T_J = 1.11W • 43°C/W + 25°C = 73°C
3617fa
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