LTC3617_15 Datasheet, PDF (18/20 Pages) Linear Technology – 6A Monolithic Synchronous Step-Down Regulator for DDR Termination

LTC3617
Typical Applications
0.75V, ±6A DDR Termination Using a 1MHz External Clock
V_IN
2.5V TO 5.5V
C_IN
22µF
×4
R_C
6k
C_C
1.5nF
VDDQ
1.5V
PGOOD
C_C1
10pF
R2
100k
R_F
24Ω
C_F
1µF
R1
365k
SV_IN
RUN
VDDQIN
RT
PV_IN
VTTR
LTC3617
SW
PGOOD
ITH
SYNC
SGND
PGND
V_FB
1MHz CLOCK
L1: VISHAY IHLP-2525CZ-01 330nH
L1
0.33µH
3617 TA03a
V_REF
0.75V
C_{O1 ±10mA}
0.1µF
VTT
0.75V
C_{O2 ±6A}
100µF
External Start-Up
Output Tracking Up/Down
500mV/DIV
VDDQ
V_REF/VTT
2ms/DIV
3617 TA03b
500mV/DIV
VDDQ
V_REF/VTT
4ms/DIV
3617 TA03c
Package Description
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-1833 Rev Ø)
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
3.65 ± 0.05
1.65 ± 0.05
0.70 ±0.05
3.00 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
R = 0.05 TYP
1.50 REF
23 24
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.40 ± 0.10
1
2
5.00 ± 0.10
0.25 ±0.05
0.50 BSC
3.50 REF
PACKAGE OUTLINE
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.50 REF
3.65 ± 0.10
1.65 ± 0.10
0.200 REF
0.00 – 0.05
(UDD24) QFN 0808 REV Ø
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3617fa
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