LTC3404IMS8 Datasheet, PDF (7/16 Pages) Linear Technology – 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator

W
FU CTIO AL DIAGRA
PLL LPF
8
SYNC/MODE
7
BURST
DEFEAT ^Y
X
Y = “0” ONLY WHEN X IS A CONSTANT “1”
SLOPE
COMP
VCO
OSC
V_IN
0.8V
0.6V –
3
+
V_FB
FREQ
SHIFT
V_REF +
0.8V
– ^EA
g_m = 0.5m ^Ω
V_IN SLEEP
V_IN
V_IN
RUN
1
0.8V REF
–
OVDET
0.85V +
SHUTDOWN
0.55V
2 I_TH
– ^EN _SLEEP
+
BURST
SQ
RQ
RS LATCH
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
I_COMP
ANTI-
SHOOT-
THRU
I_RCMP
LTC3404
6 V_IN
6Ω
P-CH P-CH
5 SW
N-CH
4 GND
3404 BD
U
OPERATIO
Main Control Loop
The LTC3404 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel MOS-
FET) and synchronous (N-channel MOSFET) switches are
internal. During normal operation, the internal top power
MOSFET is turned on each clock cycle when the oscillator
sets the RS latch, and turned off when the current com-
parator, I_COMP, resets the RS latch. The peak inductor
current at which I_COMP resets the RS latch is controlled by
the voltage on the I_TH pin, which is the output of error
amplifier EA. The V_FB pin, described in the Pin Functions
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases, it causes a slight decrease in the feedback
voltage, V_FB, relative to the 0.8V internal reference, which
in turn, causes the I_TH voltage to increase until the average
inductor current matches the new load current. While the
top MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse as indicated by
the current reversal comparator I_RCMP, or the beginning of
the next clock cycle.
Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC3404 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V_IN or connect it to a logic high
(V_SYNC/MODE > 1.5V). To disable Burst Mode operation and
enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The ad-
vantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.
3404fb
7