LTC3404IMS8 Datasheet, PDF (13/16 Pages) Linear Technology – 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator

LTC3404
APPLICATIO S I FOR ATIO
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R_DS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (ΔI_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ΔI_LOAD also begins to charge or
discharge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady-
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stabil-
ity problem. The internal compensation provides adequate
compensation for most applications. But if additional
compensation is required, the I_TH pin can be used for
external compensation using R_C, C_C1 as shown in
Figure 7. (The 47pF capacitor, C_C2, is typically needed for
noise decoupling.)
A second, more severe transient is caused by switching in
loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
C_C2
OPTIONAL
R_C ^CC1
R2
R1
LTC3404
1
RUN
8
PLL LPF
2
7
I_TH SYNC/MODE
3
V_FB
V_{IN 6}
4
GND
5
SW
C_{IN +}
BOLD LINES INDICATE
HIGH CURRENT PATHS
+
L1
+
+
V_OUT V_IN
C_OUT
Figure 7. LTC3404 Layout Diagram
––
3404 F07
Thus, a 10μF capacitor charging to 3.3V would require a
250μs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3404. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC3404 signal ground consists of the resistive
divider, the optional compensation network (R_C and
C_C1) and C_C2. The power ground consists of the (–)
plate of C_IN, the (–) plate of C_OUT and Pin 4 of the
LTC3404. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star-
ground configuration.
2. Does the V_FB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C_OUT and signal ground.
3. Does the (+) plate of C_IN connect to V_IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node SW away from sensitive small
signal nodes.
Design Example
As a design example, assume the LTC3404 is used in a
single lithium-ion battery-powered cellular phone applica-
tion. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
L
=
1
(^f)(^ΔI_L
)
V_OUT
⎛
⎝⎜
1−
V_OUT
V_IN
⎞
⎠⎟
(3)
3404fb
13