LTC3404IMS8 Datasheet, PDF (11/16 Pages) Linear Technology – 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator

LTC3404
APPLICATIO S I FOR ATIO
Phase-Locked Loop and Frequency Synchronization
The LTC3404 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 1MHz to 1.7MHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the har-
monics of the V_CO center frequency. The PLL hold-in range
Δf_H is equal to the capture range, Δf_H = Δf_C = 300kHz and
– 400kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V_{PPL LPF} (V)
3404 • F04
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
PHASE
2.4V
DETECTOR
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
R_LP
C_LP
PLL LPF
VCO
3404 F05
Figure 5. Phase-Locked Loop Block Diagram
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.
If the external frequency (V_SYNC/MODE) is greater than
1.4MHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 1.4MHz, current is sunk
continuously, pulling down the PLL LPF pin. If the
external and internal frequencies are the same but exhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla-
tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor C_LP holds the voltage.
The loop filter components C_LP and R_LP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP = 10k and C_LP is 2200pF to
0.01μF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V_{PLL LPF} pin.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3404 circuits: V_IN quiescent current and I²R
losses. The V_IN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I²R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
3404fb
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