LTC3831 Datasheet, PDF (6/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831
TYPICAL PERFOR A CE CHARACTERISTICS
PV_CC Supply Current
vs Gate Capacitance
50
T_A = 25°C
40
PV_CC1,2 = 12V
30
20
PV_CC1,2 = 5V
10
0
0 1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
TG Rise/Fall Time
vs Gate Capacitance
200
T_A = 25°C
180
160
140
120
t_f AT PV_CC1,2 = 5V
100
t_r AT PV_CC1,2 = 5V
80
60
40
t_f AT PV_CC1,2 = 12V
20
t_r AT PV_CC1,2 = 12V
0
0 1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT TG AND BG (nF)
3831 G21
Transient Response
V_OUT
50mV/DIV
I_LOAD
2A/DIV
50µs/DIV
3831 G22.tif
PI FU CTIO S
TG ( Pin 1): Top Driver Output. Connect this pin to the gate
of the upper N-channel MOSFET, Q1. This output swings
from PGND to PV_CC1. It remains low if BG is high or during
shutdown mode.
PV_CC1 (Pin 2): Power Supply Input for TG. Connect this pin
to a potential of at least V_IN + V_GS(ON)(Q1). This potential
can be generated using an external supply or a simple
charge pump connected to the switching node between
the upper MOSFET and the lower MOSFET.
PGND (Pin 3): Power Ground. Both drivers return to this
pin. Connect this pin to a low impedance ground in close
proximity to the source of Q2. Refer to the Layout Consid-
eration section for more details on PCB layout techniques.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3831.
R^–, R⁺ (Pins 5, 7): These two pins connect to the internal
resistor divider that generate the internal ratiometric ref-
erence for the error amplifier. The reference voltage is set
at 0.5 • (V_R+ – V_R–).
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external resis-
tor divider. The FB pin is servoed to the ratiometric
6
reference under closed-loop conditions. The LTC3831 can
operate with a minimum V_FB of 1.1V and maximum V_FB of
(V_CC – 1.75V).
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100µs puts the LTC3831 into
shutdown mode. In shutdown, TG and BG go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also double as
an external clock input to synchronize the internal oscilla-
tor with an external clock.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, C_SS, to implement a soft-start function. If the
LTC3831 goes into current limit, C_SS is discharged to
reduce the duty cycle. C_SS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10): External Compensation. This pin inter-
nally connects to the output of the error amplifier and input
of the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
3831f