LTC3831 Datasheet, PDF (18/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831
APPLICATIO S I FOR ATIO
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 5A.
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3831. This helps to minimize internal ground dis-
turbances in the LTC3831 and prevents differences in
ground potential from disrupting internal circuit operation.
This connection should then tie into the ground plane at
a single point, preferably at a fairly quiet point in the circuit
such as close to the output capacitors. This is not always
practical, however, due to physical constraints. Another
reasonably good point to make this connection is between
the output capacitors and the source connection of the
bottom MOSFET Q2. Do not tie this single point ground in
the trace run between the Q2 source and the input capaci-
tor ground, as this area of the ground plane will be very
noisy.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V_CC, PV_CC1 and PV_CC2 decoupling capacitors should
be as close to the LTC3831 as possible. The 4.7µF and 1µF
bypass capacitors shown at V_CC, PV_CC1 and PV_CC2 will help
provide optimum regulation performance.
5. The (+) plate of C_IN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An addi-
tional 1µF ceramic capacitor between V_IN and power ground
is recommended.
6. The V_FB pin is very sensitive to pickup from the switch-
ing node. Care should be taken to isolate V_FB from possible
capacitive coupling to the inductor switching signal.
7. In a typical SSTL application, if the R⁺ pin is to be con-
nected to V_DDQ, which is also the main supply voltage for
the switching regulator, do not connect R⁺ along the high
current flow path; it should be connected to the SSTL in-
terface supply output. R^– should be connected to the inter-
face supply GND.
8. Kelvin sense I_MAX and I_FB at Q1’s drain and source pins.
3831f
18