LTC3831 Datasheet, PDF(16/20 Page) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

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LTC3831 Datasheet, PDF (16/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

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LTC3831

APPLICATIO S I FOR ATIO

LTC3831 applications. OS-CON electrolytic capacitors

from Sanyo and other manufacturers give excellent per-

formance and have a very high performance/size ratio for

electrolytic capacitors. Surface mount applications can

use either electrolytic or dry tantalum capacitors. Tanta-

lum capacitors must be surge tested and specified for use

in switching power supplies. Low cost, generic tantalums

are known to have very short lives followed by explosive

deaths in switching power supply applications. Other

capacitor series that can be used include Sanyo POSCAPs

and the Panasonic SP line.

A common way to lower ESR and raise ripple current

capability is to parallel several capacitors. A typical LTC3831

application might exhibit 5A input ripple current. Sanyo

OS-CON capacitors, part number 10SA220M (220ÂµF/10V),

feature 2.3A allowable ripple current at 85Â°C; three in

parallel at the input (to withstand the input ripple current)

meet the above requirements. Similarly, Sanyo POSCAP

4TPB470M (470ÂµF/4V) capacitors have a maximum rated

ESR of 0.04â¦, three in parallel lower the net output

capacitor ESR to 0.013â¦.

Feedback Loop Compensation

The LTC3831 voltage feedback loop is compensated at the

COMP pin, which is the output node of the error amplifier.

The feedback loop is generally compensated with an RC +

C network from COMP to GND as shown in Figure 9a.

Loop stability is affected by the values of the inductor, the

output capacitor, the output capacitor ESR, the error

amplifier transconductance and the error amplifier com-

pensation network. The inductor and the output capacitor

create a double pole at the frequency:

[ ] fLC = 1/ 2Ï (LO)(COUT)

The ESR of the output capacitor and the output capacitor

value form a zero at the frequency:

[ ] fESR = 1/ 2Ï(ESR)(COUT)

The compensation network used with the error amplifier

must provide enough phase margin at the 0dB crossover

frequency for the overall open-loop transfer function. The

zero and pole from the compensation network are:

fZ = 1/[2Ï(RC)(CC)] and

fP = 1/[2Ï(RC)(C1)] respectively.

Figure 9b shows the Bode plot of the overall transfer

function.

Although a mathematical approach to frequency compen-

sation can be used, the added complication of input and/or

output filters, unknown capacitor ESR, and gross operat-

ing point changes with input voltage, load current varia-

tions, all suggest a more practical empirical method. This

can be done by injecting a transient current at the load and

using an RC network box to iterate toward the final values,

or by obtaining the optimum loop response using a

network analyzer to find the actual loop poles and zeros.

LTC3831

COMP

ERR

VFB

VTT

VREF

3831 F09a

Figure 9a. Compensation Pin Hook-Up

fSW = LTC3831 SWITCHING

FREQUENCY

fCO = CLOSED-LOOP CROSSOVER

FREQUENCY

20dB/DECADE

fLC

fESR

fCO

FREQUENCY

3830 F10b

Figure 9b. Bode Plot of the LTC3831 Overall Transfer Function

3831f

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