LTC3831 Datasheet, PDF (12/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831
APPLICATIO S I FOR ATIO
Q2. This circuit provides 2V_IN – V_F to PV_CC1 while Q1 is ON
and V_IN – V_F while Q1 is OFF where V_F is the forward voltage
of the Schottky diode. Ringing at the drain of Q2 can cause
transients above 2V_IN at PV_CC1; if V_IN is higher than 7V, a
12V zener diode should be included from PV_CC1 to PGND
to prevent transients from damaging the circuitry at PV_CC1
or the gate of Q1.
For applications with a lower V_IN supply, a tripling charge
pump circuit shown in Figure 7 can be used to provide 2V_IN
and 3V_IN gate drive for the external top and bottom
MOSFETs respectively. This circuit provides 3V_IN – 3V_F to
PV_CC1 while Q1 is ON and 2V_IN – 2V_F to PV_CC2 where V_F is
the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
provide more than 3V_IN at PV_CC1; a 12V zener diode should
be included from PV_CC1 to PGND to prevent transients
from damaging the circuitry at PV_CC1 or the gate of Q1.
The charge pump capacitors for PV_CC1 refresh when the
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the soft-
start capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low V_CC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 overcomes this problem by sensing the
PV_CC1 voltage when TG is high. If PV_CC1 is less than 2.5V
above V_CC, the maximum TG duty cycle is reduced to 70%
by clamping the COMP pin at 1.8V (Q_C in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
D_Z
1N5817
12V
1N5242
1N5817
V_IN
1N5817
10µF
PV_CC2
PV_CC1
TG
BG
0.1µF
0.1µF
Q1
L_O
V_OUT
+
Q2
C_OUT
LTC3831
3831 F07
Figure 7. Tripling Charge Pump
For applications using an external supply to power PV_CC1,
this supply must also be higher than V_CC by at least 2.5V
to ensure normal operation.
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, V_REF,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R⁺ and R^– pins
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R⁺ and R^–.
The LTC3831 can operate with a minimum V_FB of 1.1V and
maximum V_FB of (V_CC – 1.75V). With R^– connected to
GND, this gives a V_R+ input range of 2.2V to (2 • V_CC –
3.5V). If V_R+ is higher than the permitted input voltage,
increase the V_CC voltage to raise the input range.
In a typical DDR memory termination application as shown
in Figure 1, R⁺ is connected to V_DDQ, the supply voltage of
the interface, and R^– to GND. The output voltage V_TT is
connected to the FB pin, so V_TT = 0.5 • V_DDQ.
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to V_TT and FB
pin. Figure 8 shows an application that generates a V_TT of
0.6 • V_DDQ.
3831f
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