LTC3625-1_15 Datasheet, PDF (6/16 Pages) Linear Technology – 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing

LTC3625/LTC3625-1
Typical Performance Characteristics
T_A = 25°C, L1 = 3.3µH, L2 = 3.3µH, C_IN = 10µF, C_TOP = C_BOT , LTC3625 unless otherwise specified.
Charge Profile Into Matched
SuperCaps
6
V_IN = 3.6V, V_SEL = 3.6V
4
R_PROG = 143k
C_TOP = C_BOT = 10F
2
V_OUT
V_MID
SINGLE INDUCTOR APPLICATION
0
6
V_OUT
4
V_MID
2
0
DUAL INDUCTOR APPLICATION
0 20 40 60 80 100 120 140
TIME (SECONDS)
3625 G16
Charge Profile with C_BOT > C_TOP
6
V_IN = 3.6V, V_SEL = 3.6V
4
R_PROG = 143k
C_TOP = 10F, C_BOT = 50F
V_OUT
V_MID
2
SINGLE INDUCTOR APPLICATION
0
6
V_OUT
4
V_MID
2
0
DUAL INDUCTOR APPLICATION
0
50 100 150 200 250
TIME (SECONDS)
3625 G17
Charge Profile with C_TOP > C_BOT
6
V_IN = 3.6V, V_SEL = 3.6V
4
R_PROG = 143k
C_TOP = 50F, C_BOT = 10F
2
V_OUT
V_MID
SINGLE INDUCTOR APPLICATION
0
6
V_OUT
4
V_MID
2
0
DUAL INDUCTOR APPLICATION
0 50 100 150 200 250 300 350
TIME (SECONDS)
3625 G18
Pin Functions
SW1 (Pin 1): Switch Pin for the Buck Regulator. External
inductor connects between SW1 pin and V_MID.
V_IN (Pin 2): Input Voltage Pin. Bypass to GND with a 10µF
or larger ceramic capacitor.
CTL (Pin 3): Logic Input. CTL sets the charge mode of the
LTC3625/LTC3625-1. A logic high at CTL programs the part
to operate with a single inductor; a logic low programs
the part to operate with two inductors. In the 2-inductor
application the capacitor stack will charge approximately
twice as quickly. CTL is a high impedance input and must
be tied to either V_IN or GND. Do not float.
V_SEL (Pin 4): Logic Input. V_SEL selects the output volt-
age of the LTC3625/LTC3625-1. A logic low at V_SEL sets
the per-cell maximum voltage to 2.45V/2.05V (V_OUT =
4.8V/4.0V); a logic high sets the per-cell maximum volt-
age to 2.70V/2.30V (V_OUT = 5.3V/4.5V). When the part is
enabled, V_SEL has a 4.5MΩ internal pull-down resistor; if
EN is low, then V_SEL is a high impedance input pin.
EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1.
Active high. Has a 4.5MΩ internal pull-down resistor.
PROG (Pin 6): Charge Current Program Pin. Connecting a
resistor from PROG to ground programs the buck output
current. This pin servos to 1.2V.
PFI (Pin 7): Input to the Power Fail Comparator. This pin
connects to an external resistor divider between V_IN and
GND. If this functionality is not desired, PFI should be
tied to V_IN.
PFO (Pin 8): Open-Drain Output of the Power-Fail Compara-
tor. The part pulls this pin low if V_IN is less than a value
programmed by an external divider. This pin is active low
in shutdown mode. If this functionality is not desired PFO
should be left unconnected.
PGOOD (Pin 9): Logic Output. This is an open-drain
output which indicates that V_OUT has settled to its final
value. Upon start-up, this pin remains low until the output
voltage, V_OUT , is within 92.5% (typical) of its final value.
Once V_OUT is valid, PGOOD becomes high impedance. If
V_OUT falls to 89.5% (typical) of its correct regulation level,
PGOOD is pulled low. PGOOD may be pulled up through
an external resistor to an appropriate reference level. This
pin is active low in shutdown mode.
3625f