LTC3625-1_15 Datasheet, PDF (13/16 Pages) Linear Technology – 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing

LTC3625/LTC3625-1
Applications Information
board ground. Failure to make thermal contact between
the exposed pad on the backside of the package and the
copper board will result in higher thermal resistances.
Furthermore, due to its potentially high frequency switch-
ing circuitry, it is imperative that the input capacitor,
inductors, and output bypass capacitors be as close to
the LTC3625/LTC3625-1 as possible, and that there be an
unbroken ground plane under the IC and all of its external
high frequency components. High frequency currents, such
as the V_IN and V_OUT currents on the LTC3625/LTC3625-1,
tend to find their way along the ground plane in a myriad of
paths ranging from directly back to a mirror path beneath
the incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the highest possible layer of the PC board.
Any board resistance between inductor(s) and the posi-
tive terminal of C_BOT will add to the capacitors internal
ESR. Likewise, any resistance between the V_OUT pin
and the positive terminal of C_TOP will add to its internal
ESR. Any added resistance to the capacitors will reduce
the effective charging efficiency. In the case of C_BOT this
resistance can be kelvined out by a dedicated voltage
sense trace from the V_MID pin to a point halfway between
the bottom plate of C_TOP and the top plate of C_BOT . In the
case of C_TOP , however, it is even more critical to keep any
resistance in the connection to a minimum. Excessive
series resistance may cause the part to duty cycle in and
out of sleep or prematurely shut down the boost, due to
the voltage seen at the part being equal to V_OUT + I_OUT •
ESR. Likewise the C_BOT supercapacitor should be provided
with a low impedance contact to the ground plane with
an unbroken, low impedance, path back to the backside
of the LTC3625/LTC3625-1 package.
When laying out the printed circuit, the following check-
list should be used to ensure proper operation of the
LTC3625/LTC3625-1.
1. Are the bypass capacitors at V_IN and V_OUT as close as
possible to the LTC3625/LTC3625-1? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers. Minimizing inductance from these
capacitors to the LTC3625/LTC3625-1 is a top priority.
2. Are the C_BOT bypass capacitor and the power inductor(s)
closely connected? The (–) terminal of the C_BOT bypass
capacitor returns current to the GND plane, and then
back to C_IN.
3. Keep sensitive components away from the SW pins.
4. Keep the current carrying traces from V_OUT to C_TOP and
the inductors to C_BOT to a minimum.
Typical Applications
450mA Charge Current 1-Inductor Application
V_IN*
2.7V TO 5.5V
C1
10µF
V_IN
V_OUT
LTC3625-1
SW1
L1 3.3µH
V_IN
V_IN
R1
287k
R2
100k
EN
CTL
V_SEL
PGOOD
PFO
PFI
PROG
R3
71.5k
SW2
V_MID
GND
3625 TA03
*25mA MINIMUM LOAD REQUIRED ON V_IN
V_OUT
4.0V/4.5V
C2 ≥ 0.1F
C3 ≥ 0.1F
3625f
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