LTC3625-1_15 Datasheet, PDF (3/16 Pages) Linear Technology – 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing

LTC3625/LTC3625-1
Electrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V, R_PROG = 143k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
I_VIN
I_VOUT
V_PROG
h_PROG
I_BUCK
I_MAX
Input Operating Current,
I_SW1 = I_SW2 = 0µA, No Switching
CTL = V_IN, V_MID = 1.5V, V_OUT = 2.5V (Boost Only)
CTL = V_IN, V_MID = 1.5V, V_OUT = 3.5V (Buck Only)
CTL = 0, V_MID = 1.5V, V_OUT = 2.5V (Buck and Boost)
135
200
275
400
365
530
Input Sleep Current
V_IN = 5.5V, V_OUT = 5.4V
V_IN = 3.6V, V_OUT = 5.4V
23
35
8
15
Input SD Current
V_OUT = 0V
0
1
V_OUT SD Current
V_OUT = 5.4V
0
1
V_OUT Sleep Current
V_OUT = 5.4V, V_IN = 3.6V, EN = V_IN
V_OUT = 5.4V, V_IN = 5.5V, EN = V_IN
17
25
1
2.5
PROG Servo Voltage
V_OUT = 3.5V, V_MID = 1.5V
l 1.17
1.2
1.23
Ratio of Measured I_PROG Current to
I_BUCK Programmed Current
118,000
Programmed Buck Charge Current R_PROG = 143k (Note 5)
R_PROG = 71.5k (Note 5)
0.88
0.99
1.10
1.76
1.98
2.20
Maximum Programmed Charge
Current
R_PROG = 0Ω (Fault Condition) (Note 5)
1.98
2.65
3.31
V_MID(GOOD) V_MID Voltage Where the Boost
1.35
Regulator is Enabled
V_MID(GOOD) Hysteresis
150
V_TRICKLE
V_OUT Voltage Above Which Boost V_OUT Rising
V_MID
Regulator Will Exit Trickle Charge
Mode and Enter Normal Charge
Mode
I_PEAK(BUCK)
I_VALLEY(BUCK)
I_PEAK(BOOST)
V_TRICKLE Falling Hysteresis
Buck Charge Current Peak
Buck Charge Current Valley
Boost Charge Current Peak
I_{VALLEY(BOOST)} Boost Charge Current Valley
R_PMOS
R_NMOS
I_LEAK
Maximum Boost Valley Time
PMOS On-Resistance
NMOS On-Resistance
SW Pin Leakage Current for SW1,
SW2
V_OUT = 3V, V_MID = 2V (Note 5)
V_OUT = 1V, V_MID = 2V (Note 5)
V_OUT = 3V, V_MID = 2V
V_OUT = 1V, V_MID = 2V
V_OUT = 1V, V_MID = 2V
EN = 0V
50
1.1 • I_BUCK
0.9 • I_BUCK
1.59
2.12
2.65
200
1.41
1.88
2.35
0
6.5
120
100
1
V_PFI
PFI Falling Threshold
PFI Hysteresis
l 1.17
1.2
1.23
15
I_PFI
Pin Leakage Current for PFI Pin
Logic (EN, CTL, V_SEL, PGOOD, PFO)
V_IL
Input Low Logic Voltage
V_IH
Input High Logic Voltage
I_IL, I_IH
Input Low, High Current for CTL
R_PD
EN Pin Pull-Down Resistance
V_SEL Pin Pull-Down Resistance
V_OL
Output Low Logic Voltage
I_OH
Logic High Leakage Current
PGOOD Rising Threshold
PGOOD Hysteresis
EN, CTL, V_SEL Pins
EN, CTL, V_SEL Pins
CTL
EN = V_IN
PGOOD, PFO Pins; Sinking 5mA
PGOOD, PFO Pins; Pin Voltage = 5V
V_OUT as a Percentage of Final Target
∆V_OUT as a Percentage of Final Target
0
30
l
0.4
l 1.2
1
4.5
4.5
l
70
200
1
90
92.5
95
3
UNITS
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
A
A
A
V
mV
V
mV
A
A
A
mA
A
mA
µs
mΩ
mΩ
µA
V
mV
nA
V
V
µA
MΩ
MΩ
mV
µA
%
%
3625f