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LTC3625-1_15 Datasheet, PDF (15/16 Pages) Linear Technology – 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing
Typical Applications
12V
LT1737 FLYBACK 4
6
•
10
DC-A
7
•
DC-B
2 • 11
8
LT1737
•
GND
DC-C
12
LTC3625/LTC3625-1
12V Power Ride-Through
VIN
VOUT
CTL
SW1
LTC3625
EN
SW2
GND
VSEL
VMID
PROG
*
L1 3.3µH
L2 3.3µH
R1
143k
VIN
VOUT
CTL LTC3625 SW1
EN
GND
SW2
VSEL
VMID
PROG
*
L3 3.3µH
L4 3.3µH
R2
143k
VIN
VOUT
CTL
SW1
LTC3625
EN
SW2
GND
VMID
VSEL
PROG
L5 3.3µH
L6 3.3µH
R3
143k
IDEAL DIODE
LTC4355
FDS3672
M1
IRF7424
C1
100F
FDS3672
UV
C2
DETECTOR
100F
*EXPOSED PAD TO
BE CONNECTED TO A
THERMAL PAD ISOLATED
FROM THE SYSTEM GROUND
C3
100F
C4
100F
C5
100F
C6
100F
DC/DC
VIN
VOUT
1.8V
LTM4601A
GND GND
GND
Package Description
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.70 p0.05
3.60 p0.05
2.20 p0.05
3.30 p0.05
1.70 p 0.05
PIN 1
TOP MARK
PACKAGE (NOTE 6)
OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.200 REF
4.00 p0.10
(2 SIDES)
R = 0.115
7
TYP
0.40 p 0.10
12
R = 0.05
TYP
3.00 p0.10
(2 SIDES)
3.30 p0.10
1.70 p 0.10
0.75 p0.05
6
0.25 p 0.05
2.50 REF
1
0.50 BSC
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0806 REV D
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3625f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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