LTC3589-2_15 Datasheet, PDF (37/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589/LTC3589-1/
LTC3589-2
OPERATION
I²C Sub-Addressed Writing
The LTC3589 has 14 writable command registers for
control inputs. They are accessed by the I²C port via a
sub-addressed writing system.
Each write cycle of the LTC3589 consists of a series of
three or more bytes beginning with the LTC3589 write ad-
dress. The second byte is the sub address of the command
register being written to. The sub address is a pointer to the
register where the data in the third byte will be stored. The
third byte is the data to be written to the just-received sub
address. Continue alternating sub address and data bytes
to write multiple registers in a single START sequence.
I²C Bus Write Operation
The master initiates communication with the LTC3589
with a START condition and the LTC3589 write address.
If the address matches that of the LTC3589, the LTC3589
returns an acknowledge pulse. The master should then
deliver the sub address. Again the LTC3589 acknowl-
edges and the cycle is repeated for the data byte. The
data byte is transferred to an internal holding latch
upon the return of its acknowledge by the LTC3589.
Continue writing sub address and data pairs into the
holding latches. Addressing the LTC3589 is not required
for each sub address and data pair. If desired a REPEAT-
START condition may be initiated by the master where
another device on the I²C bus is addressed. The LTC3589
remembers the valid data it has received. Once all the
devices on the I²C have been addressed and sent valid
data and a global STOP has been sent, the LTC3589 will
update its command latches with the data it has received.
I²C Sub-Addressed Reading
The LTC3589 I²C interface supports random address
reading of the I²C command and status registers. Before
reading a register, the registers sub address must be
written. Send a START condition followed by the LTC3589
write address followed by the sub address of the register
to be read. The sub address is now stored as a pointer to
the register. Send a REPEAT-START condition followed
by the LTC3589 read address. Following the acknowledg-
ment of its read address the LTC3589 returns one bit of
information for each of the next 8 clock cycles. A STOP
condition is not required for the read operation. The read
sub address is stored until a new sub address is written.
Verify the data written to the internal data hold latches
prior to committing data to the command registers by
reading back the data before sending a STOP condition.
Continuously poll a register by repeatedly sending a START
condition followed by the LTC3589 read address, and then
clocking the data out after the read address acknowledge.
I²C Command and Status Registers
Table 17 and Table 18 show the LTC3589 I²C command
and status registers. System control register (SCR1) sets
the operating modes of the switching regulators. Each
step-down switching regulator has pulse-skipping, Burst
Mode operation, or forced continuous operation. The
buck-boost switching regulator can be put in continuous
or Burst Mode operation.
The output voltage enable (OVEN) command register
controls the individual enables of each regulator. When
OVEN[7] is set to a logic LOW value, bits OVEN[6-0] are
ORed with their respective enable pins. When OVEN[7]
is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2,
and EN_LDO34, are ignored and the LTC3589 regulators
respond only to the OVEN register. When the regulators
are configured in a hard wired power-up sequence, setting
OVEN[7] allows software control of individual regulators.
When the PWR_ON pin is pulled LOW all bits in the OVEN
register are reset to POR state of 0x00.
System control register 2 (SCR2) controls the operation of
the regulator start-up and regulator power good (PGOOD)
hard shutdown operation. Command register bit SCR2[7]
controls the LTC3589 behavior during an extended PGOOD
fault condition longer than 14ms. Bit SCR2[7] does not
alter PGOOD status reporting by the IRQ pin or IRQSTAT
status register. The bits in SCR2[6-0] control whether a
regulator will wait to turn on when its output is greater
than 300mV. Default POR LOW cause the LTC3589 and
LTC3589-1 regulators to wait for the output to discharge
to less than 300mV. Default POR low of the LTC3589-2
allows the regulators to start at any output voltage.
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