LTC3589-2_15 Datasheet, PDF (29/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589/LTC3589-1/
LTC3589-2
OPERATION
Writing a 0 or 1 to the odd bits of voltage change control
register VCCR selects DAC output voltages V1 or V2,
respectively. A slew of the DAC is initiated by writing a 1
to an even bit of register VCCR. The DAC output will slew
to either voltage, V1 or V2, as selected by the odd bits of
register VCCR. Slew begins when the I²C STOP condition
is detected. At the end of the slewing operation the GO
bits in command register VCCR are cleared.
The slew rate for each regulator is set in the ramp rate
control register VRRCR. Each DAC has independent output
voltage registers, voltage register select, and slew rate and
start controls. The regulators do not have to be enabled
to change the DAC outputs.
The VSTB pin is used to set the DAC controlled output rails
to a low power standby condition. When VSTB is driven
HIGH, all four of the DAC references will immediately slew
to V2. To use VSTB to set the rails to standby voltage,
select V1 for normal rail voltages and V2 for standby rail
voltages. Drive VSTB high to immediately slew all the
DAC outputs to V2. When VSTB is driven LOW, the DAC
outputs will slew to V1.
The default power-up value of all the dynamic target voltage
registers is 11001 corresponding to a DAC output volt-
age of 0.675V. The DTV registers may be reprogrammed
prior to initiating a power-up sequence or at any time for
dynamic slewing.
When a step-down switching regulator output is slewing
down its mode is automatically switched to forced continu-
ous to enable the regulator to sink current. When LDO2 is
slewing down, a 2.5k pull-down is connected to its output.
Table 14 shows command register and feedback divider
settings to enable slewing step-down switching regulator 1
between 1.2V and 1V in 70µs. The voltage ramp rate
control register bits VRRCR[1:0] are set to 01 which selects
a ramp rate of 1.75mV/µs at the DAC output. The slew rate
at the regulator output is a function of the feedback resistor
divider gain. In this example, the slew is equal to 1.75 • (1
+ 301/499) = 2.8mV/µs. Therefore, a slew of 200mV will
take 70µs. To initiate a change from 1.2V to 1V write 11 to
voltage change control register bits VCCR[1:0]. VCCR[1]
selects target register B1DTV2 to set the regulator reference
input to 0.625V. VCCR[0] set to 1 initiates the dynamic
slew to go to the new voltage. To slew back to 1.2V write
01 to command register bits VCCR[1:0].
Table 14. Dynamic Slewing Example for Step-Down Switching
Regulator 1
COMMAND
REGISTER
V_OUT =1.2V V_OUT =1V
VRRCR[1:0]
01
01
Dynamic Slew Rate
VCCR[1]
0
1
Select DTV
B1DTV1[4:0]
B1DTV2[4:0]
11111
10101
11111
10101
Resistor Divider Shown
in Figure 3
R1 = 301kΩ
R2 = 499kΩ
Pushbutton Operation
State Event Diagram
Figure 5 shows the LTC3589 pushbutton state diagram.
Upon the first power application to the LTC3589 V_IN pin an
internal power-on reset circuit puts the pushbutton into the
power-down (PDN) state and initiates a one second timer.
The LTC3589 status pin RSTO is pulled low until one second
times out and the always-alive LDO1 is indicating power
good status. After the one second interval the pushbutton
circuit will transition to the power-off (POFF) standby state.
The LTC3589-1/LTC3589-2 powers on directly to the POFF
state bypassing the one second delay. Status pin RSTO will
be released high when LDO1 indicates power good status.
The LTC3589 will not leave the POFF state and enter the
power-up state (PUP) until ON is held LOW for at least
ON OR
PWR_ON
PUP
5 SEC
ON OR
PWR_ON
PUP
5 SEC
POFF
PON POR
1 SEC
POR
PDN
FAULT OR
PWR_ON OR
HARD RESET
LTC3589
POFF
PON
1 SEC
FAULT OR
PWR_ON OR
PDN
HARD RESET
3589 F05
LTC3589-1/LTC3589-2
Figure 5. Pushbutton Controller State Diagram
For more information www.linear.com/LTC3589
3589fg
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