LTC3589-2_15 Datasheet, PDF (28/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589/LTC3589-1/
LTC3589-2
OPERATION
Capacitor Selection
Low ESR ceramic capacitors should be used at both the
output and input supply of the buck-boost switching
regulator. Only X5R or X7R ceramic capacitors should
be used because they retain their capacitance over wider
voltage and temperature ranges than other ceramic types.
A 22µF capacitor is sufficient for the buck-boost switch-
ing regulator output. For good transient response and
stability the output capacitor should retain at least 10µF of
capacitance over operating temperature and bias voltage.
Place at least 4.7µF decoupling capacitance as close as
possible to PV_IN4 pin. Refer to Table 12 for recommended
ceramic capacitor manufacturers.
Table 12. Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay Siliconix
www.vishay.com
TDK
www.tdk.com
Slewing DAC Reference Operation
Controlling the DAC References
The three LTC3589 step-down switching regulators and
linear regulator LDO2 have programmable DAC reference
inputs. Each DAC is programmable from 0.3625V to 0.75V
in 12.5mV steps:
V_OUT =⎛⎝⎜1+ _RR21^{⎞⎠⎟} • (0.3625+BxDTVx • 0.0125)(V)
The DAC references may be commanded to independently
slew between two voltages at one of four selectable slew
rates. Table 13 summarizes the command registers used
to control slewing DAC operation.
Table 13. Slewing DAC Command Register Control Summary
COMMAND
REGISTER[BIT]
FUNCTION
VCCR[0], VCCR[2],
VCCR[4], VCCR[6]
Voltage Change Control Register
G0 / Slew
Write a 1 to Initiate a Slew to the Voltage
Selected in VCCR[1], VCCR[3], VCCR[5],
VCCR[7] Respectively.
Bits are Reset to 0 at the End of the Slew
Operation.
VCCR[1], VCCR[3],
VCCR[5], VCCR[7]
Voltage Change Control Register
Dynamic Target Select
Write a 0 to Select Voltage V1 Stored in
Registers B1DTV1[4-0], B2DTV1[4-0],
B3DTV1[4-0], L2DTV1[4-0].
Write a 1 to Select Voltage V2 in Registers
B1DTV2[4-0], B2DTV2[4-0], B3DTV2[4-0],
L2DTV2[4-0].
B1DTV1[4-0], B2DTV1[4-0], Dynamic Target Voltage 1
B3DTV1[4-0], L2DTV1[4-0] _{Five Bits Corresponding to V1 Output from}
Each DAC.
B1DTV1[5], B2DTV1[5],
B3DTV1[5], L2DTV1[5]
PGOOD Mask
Write a 1 to Continue Normal PGOOD
Operation When Slewing.
Write a 0 to Force PGOOD to Pull Low
During Slew.
B1DTV2[4-0], B2DTV2[4-0], Dynamic Target Voltage 2
B3DTV2[4-0], L2DTV2[4-0] _{Five Bits Corresponding to V2 Output from}
Each DAC.
VRRCR[1-0], VRRCR[3-2],
VRRCR[5-4], VRRCR[7-6]
Voltage Ramp Rate Control
Two Bits That Set the DAC Output Slew
Rate for Step-Down Switching Regulator
and LDO2.
Setting and Slewing the DAC Outputs
The 5-bit word in dynamic target voltage command reg-
isters B1DTV1, B2DTV1, B3DTV1, and L2DTV1 programs
reference voltage V1. The 5-bit word in command registers
B1DTV2, B2DTV2, B3DTV2, and L2DTV2 programs refer-
ence voltage V2. A resistor divider network on the output
and feedback pins of the regulators set their output voltage.
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3589fg