LTC3350_15 Datasheet, PDF (34/46 Pages) Linear Technology – High Current Supercapacitor Backup Controller and System Monitor

LTC3350
Register Descriptions
msk_mon_status (0x02)
Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an
SMBALERT.
BIT(S) BIT NAME
DESCRIPTION
0
msk_mon_capesr_active
Set the SMBALERT when there is a rising edge on mon_capesr_active
1
msk_mon_capesr_scheduled
Set the SMBALERT when there is a rising edge on mon_capesr_scheduled
2
msk_mon_capesr_pending
Set the SMBALERT when there is a rising edge on mon_capesr_pending
3
msk_mon_cap_done
Set the SMBALERT when there is a rising edge on mon_cap_done
4
msk_mon_esr_done
Set the SMBALERT when there is a rising edge on mon_esr_done
5
msk_mon_cap_failed
Set the SMBALERT when there is a rising edge on mon_cap_failed
6
msk_mon_esr_failed
Set the SMBALERT when there is a rising edge on mon_esr_failed
7
–
Reserved, write to 0
8
msk_mon_power_failed
Set the SMBALERT when there is a rising edge on mon_power_failed
9
msk_mon_power_returned
Set the SMBALERT when there is a rising edge on mon_power_returned
15:10 –
Reserved, write to 0
cap_esr_per (0x04)
10 seconds per LSB
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10
seconds. Capacitance and ESR measurements will not repeat if this register is zero.
vcapfb_dac (0x05)
CAPFBREF = 37.5mV • vcapfb_dac + 637.5mV
V_CAP Regulation Reference: This register is used to program the capacitor voltage feedback loop’s reference voltage. Only bits 3:0 are active.
vshunt (0x06)
183.5µV per LSB
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will
shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be
programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt.
cap_uv_lvl (0x07)
183.5µV per LSB
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below
this level will trigger an alarm and an SMBALERT.
cap_ov_lvl (0x08)
183.5µV per LSB
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor voltage rising above this level
will trigger an alarm and an SMBALERT.
gpi_uv_lvl (0x09)
183.5µV per LSB
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm
and an SMBALERT.
gpi_ov_lvl (0x0A)
183.5µV per LSB
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and
an SMBALERT.
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