LTC3350_15 Datasheet, PDF (12/46 Pages) Linear Technology – High Current Supercapacitor Backup Controller and System Monitor

LTC3350
Pin Functions
INTV_CC (Pin 29): Internal 5V Regulator Output. The control
circuits and gate drivers (when connected to DRV_CC) are
powered from this supply. If not connected to DRV_CC,
decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
VOUTSN (Pin 30): Input Current Limiting Amplifier Nega-
tive Input. A sense resistor, R_SNSI, between VOUTSP and
VOUTSN sets the input current limit. The maximum input
current is 32mV/R_SNSI. An RC network across the sense
resistor can be used to modify loop compensation. To
disable input current limit, connect this pin to VOUTSP.
VOUTSP (Pin 31): Backup System Supply Voltage and
Input Current Limiting Amplifier Positive Input. The voltage
across the VOUTSP and VOUTSN pins are used to regulate
input current. This pin also serves as the power supply
for the IC. The voltage at this pin is digitized and can be
read in the meas_vout register.
VOUTM5 (Pin 32): V_OUT – 5V Regulator. This pin is regu-
lated to 5V below V_OUT or to ground if V_OUT < 5V. This
rail provides power to the input current sense amplifier.
Decouple this pin with at least 1μF to V_OUT.
INFET (Pin 33): Input Ideal Diode Gate Drive Output. This
pin controls the gate of an external N-channel MOSFET
used as an ideal diode between V_IN and V_OUT. The gate
drive receives power from an internal charge pump. The
source of the N-channel MOSFET should be connected
to V_IN and the drain should be connected to VOUTSP. If
the input ideal diode MOSFET is not used, INFET should
be left floating.
V_IN (Pin 34): External DC Power Source Input. Decouple
this pin with at least 0.1μF to ground. The voltage at this
pin is digitized and can be read in the meas_vin register.
CAP_SLCT0, CAP_SLCT1 (Pins 35, 36): CAP_SLCT0 and
CAP_SLCT1 set the number of super-capacitors used.
Refer to Table 1 in the Applications Information section.
PFI (Pin 37): Power-Fail Comparator Input. When the
voltage at this pin drops below 1.17V, PFO is pulled low
and step-up mode is enabled.
PFO (Pin 38): Power-Fail Status Output. This open-drain
output is pulled low when a power fault has occurred.
PGND (Exposed Pad Pin 39): Power Ground. The exposed
pad must be connected to a continuous ground plane on
the second layer of the printed circuit board by several vias
directly under the LTC3350 for rated thermal performance.
It must be tied to the SGND pin.
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