LTC3350_15 Datasheet, PDF (17/46 Pages) Linear Technology – High Current Supercapacitor Backup Controller and System Monitor

LTC3350
Operation
Gate Drive Supply (DRV_CC)
The bottom gate driver is powered from the DRV_CC pin. It
is normally connected to the INTV_CC pin. An external LDO
can also be used to power the gate drivers to minimize
power dissipation inside the IC. See the Applications
Information section for details.
Supercapacitors lose capacitance as they age. By initially
setting the V_CAP DAC to a low setting, the final charge
voltage on the supercapacitors can be increased as they
age to maintain a constant level of stored backup energy
throughout the lifetime of the supercapacitors.
Power-Fail (PF) Comparator
Undervoltage Lockout (UVLO)
Internal undervoltage lockout circuits monitor both the
INTV_CC and DRV_CC pins. The switching controller is kept
off until INTV_CC rises above 4.3V and DRV_CC rises above
4.2V. Hysteresis on the UVLOs turn off the controller if
either INTV_CC falls below 4V or DRV_CC falls below 3.9V.
Charging is not enabled until VOUTSN is 185mV above the
supercapacitor voltage and V_IN is above the PFI threshold.
Charging is disabled when VOUTSN falls to within 90mV of
the supercapacitor voltage or V_IN is below the PFI threshold.
RT Oscillator and Switching Frequency
The RT pin is used to program the switching frequency.
A resistor, R_T, from this pin to ground sets the switching
frequency according to:
f_SW
(MHz)
=
53.5
R_T (kΩ
)
R_T also sets the scale factor for the capacitor measurement
value reported in the meas_cap register, described in the
Capacitance and ESR Measurement section of this data
sheet.
Input Overvoltage Protection
The LTC3350 has overvoltage protection on its input. If
V_IN exceeds 38.6V, the switching controller will hold both
switches off. The controller will resume switching if V_IN
falls below 37.2V.
V_CAP DAC
The feedback reference for the CAPFB servo point can be
programmed using an internal 4-bit digital-to-analog converter
(DAC). The reference voltage can be programmed from
0.6375V to 1.2V in 37.5mV increments. The DAC defaults to
full scale (1.2V) and is programmed via the vcapfb_dac register.
The LTC3350 contains a fast power-fail (PF) comparator
which switches the part from charging to backup mode in
the event the input voltage, V_IN, falls below an externally
programmed threshold voltage. In backup mode, the input
ideal diode shuts off and the supercapacitors power the load
either directly through the output ideal diode or through
the synchronous controller in step-up mode.
The PF comparator threshold voltage is programmed by
an external resistor divider via the PFI pin. The output of
the PF comparator also drives the gate of an open-drain
NMOS transistor to report the status via the PFO pin. When
input power is available the PFO pin is high impedance.
When V_IN falls below the PF comparator threshold, PFO
is pulled down to ground.
The output of the PF comparator may also be read from
the chrg_pfo bit in the chrg_status register.
Charge Status Indication
The LTC3350 includes a comparator to report the status
of the supercapacitors via an open-drain NMOS transistor
on the CAPGD pin. This pin is pulled to ground until the
CAPFB pin voltage rises to within 8% of the V_CAP DAC
setting. Once the CAPFB pin is above this threshold, the
CAPGD pin goes high impedance.
The output of this comparator may also be read from the
chrg_cappg bit in the chrg_status register.
Capacitor Voltage Balancer
The LTC3350 has an integrated active stack balancer. This
balancer slowly balances all of the capacitor voltages to
within about 10mV of each other. This maximizes the life
of the supercapacitors by keeping the voltage on each as
low as possible to achieve the needed total stack voltage.
When the difference between any two capacitor volt-
ages exceeds about 10mV, the capacitor with the largest
For more information www.linear.com/LTC3350
3350fb
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