LTC3675_15 Datasheet, PDF (31/38 Pages) Linear Technology – 7-Channel Configurable High Power PMIC

LTC3675/LTC3675-1
Applications Information
Status Byte Read Back
When either the RSTB or IRQB pin is pulled low, it indicates
to the user that a fault condition has occurred. To find out
the exact nature of the fault, the user can read the status reg-
isters. There are two status registers. One register provides
real time fault condition reporting while a second register
latches data when an interrupt has occurred. Figure 4
shows the operation of the real time and latched status
registers. The contents of the latched status register are
cleared when a CLRINT signal is issued. A PGOOD bit is
a ‘0’ if that regulator’s output voltage is more than 8%
below its programmed value.
The sub-address for the real time status register is 0Ch
and its format is as follows:
BIT7
Unused
BIT6
Unused
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
PGOOD6 PGOOD5 PGOOD4 PGOOD3 PGOOD2 PGOOD1
The sub-address for the latched status register is 0Dh and
its format is as follows:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
UV
OT
PGOOD6 PGOOD5 PGOOD4 PGOOD3
BIT1
PGOOD2
BIT0
PGOOD1
A write operation cannot be performed to either of the
status registers.
PCB Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3675/LTC3675-1:
1. The exposed pad of the package (pin 45) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. All the input supply pins must be tied together and each
supply pin should have a decoupling capacitor.
3. The switching regulator input supply pins and their re-
spective decoupling capacitors should be kept as short
as possible. The GND side of these capacitors should
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