LTC3675_15 Datasheet, PDF (21/38 Pages) Linear Technology – 7-Channel Configurable High Power PMIC

LTC3675/LTC3675-1
Operation
Power-Up and Power-Down via Enable Pin or I²C
With the LTC3675/LTC3675-1 in its off state, a regulator
can be enabled either via its enable pin or I²C. In Figure 2c,
buck regulator 1 is enabled via its enable pin at time t₁.
The WAKE pin goes HIGH for 5 seconds and at t₂ is pulled
LOW. The buck regulator stays enabled until time t₃ when
a hard reset command is issued via I²C. The buck regula-
tor powers down and stays off for 1 second. At time t₄,
the LTC3675/LTC3675-1 exit from the power down state.
Since the buck regulator 1 is still enabled via its enable
pin, it powers back up. WAKE also gets pulled HIGH for
5 seconds. The RSTB pin gets pulled HIGH 200ms after
the buck regulator 1 is in its PGOOD state.
LED Current Programming
The LED current is primarily controlled through the LED
DAC register at I²C sub-address 8. This register controls
an 8 bit current DAC. A 20k resistor placed between the
LED_FS pin and ground provides a current reference for
the DAC which results in 98µA of programmed LED current
per LSB. For example, programming a LED DAC register
code of 64h will result in a LED current of 9.8mA and a
full-scale setting of FFh will result in a LED current of 25mA.
The 2xFS bit which is bit 3 of the LED configuration register
at sub-address 7 effectively doubles the programmed LED
current. With a 20k resistor from LED_FS to ground each
LSB will be 196µA. Programming a LED DAC register
code of 64h will result in a LED current of 19.6mA and
a full-scale setting of FFh will result in an LED current of
50mA. The 2xFS mode is only intended for use when the
output voltage is below 20V.
I²C Interface
The LTC3675/LTC3675-1 may communicate with a bus
master using the standard I²C 2-wire interface. The timing
diagram (Figure 3) shows the relationship of the signals
on the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3675/LTC3675-1 are
both a slave receiver and slave transmitter. The I²C control
signals, SDA and SCL are scaled internally to the DV_CC
supply. DV_CC should be connected to the same power
supply as the bus pull-up resistors.
The I²C port has an undervoltage lockout on the DV_CC pin.
When DV_CC is below 1V, the I²C serial port is cleared and
the LTC3675/LTC3675-1 registers are set to their default
configurations.
I²C Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
00
START
SDA
00
ADDRESS
0100
WR
10
DATA BYTE A
A7 A6 A5 A4 A3 A2 A1 A0
DATA BYTE B
B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 0 1 0 ACK
ACK
ACK
STOP
SCL
123456789123456789123456789
SDA
t_LOW
t_{SU, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_r
t_f
t_{HD, DAT}
t_{SU, STA}
t_{HD, STA}
t_SP
REPEATED START
CONDITION
Figure 3. I²C Bus Operation
For more information www.linear.com/LTC3675
t_BUF
t_{SU, STO}
36751 F03
STOP
CONDITION
START
CONDITION
36751fc
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