LTC3675_15 Datasheet, PDF (22/38 Pages) Linear Technology – 7-Channel Configurable High Power PMIC

LTC3675/LTC3675-1
Operation
I²C Start and Stop Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from high to low while
SCL is high. The master may transmit either the slave
write or the slave read address. Once data is written to
the LTC3675/LTC3675-1, the master may transmit a STOP
condition which commands the LTC3675/LTC3675-1 to
act upon its new command set. A STOP condition is sent
by the master by transitioning SDA from low to high
while SCL is high. The bus is then free for communication
with another I²C device.
I²C Byte Format
Each byte sent to or received from the LTC3675/LTC3675-1
must be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3675/
LTC3675-1 most significant bit (MSB) first.
I²C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3675/LTC3675-1
are written to (write address), it acknowledges its write
address as well as the subsequent two data bytes. When
it is read from (read address), the LTC3675/LTC3675-1
acknowledge its read address only. The bus master should
acknowledge receipt of information from the LTC3675/
LTC3675-1.
An acknowledge (active LOW) generated by the LTC3675/
LTC3675-1 lets the master know that the latest byte of
information was received. The acknowledge related clock
pulse is generated by the master. The master releases the
SDA line (HIGH) during the acknowledge clock cycle. The
LTC3675/LTC3675-1 pull down the SDA line during the
write acknowledge clock pulse so that it is a stable LOW
during the HIGH period of this clock pulse.
When the LTC3675/LTC3675-1 are read from, it releases
the SDA line so that the master may acknowledge receipt
of the data. Since the LTC3675/LTC3675-1 only transmit
one byte of data during a read cycle, a master not acknowl-
edging the data sent by the LTC3675/LTC3675-1 has no
I²C specific consequence on the operation of the I²C port.
I²C Slave Address
The LTC3675 responds to a 7-bit address which has been
factory programmed to b’0001001[R/WB]’. The LSB of
the address byte, known as the read/write bit, should be
0 when writing data to the LTC3675 and 1 when reading
data from it. Considering the address as an 8-bit word,
the write address is 12h and the read address is 13h. The
LTC3675-1 is factory programmed to b‘0110100[R/WB]’.
Its write address is 68h and the read address is 69h.
The LTC3675/LTC3675-1 will acknowledge both the read
and write addresses.
I²C Sub-Addressed Writing
The LTC3675/LTC3675-1 have twelve command registers
for control input. They are accessed by the I²C port via a
sub-addressed writing system.
A single write cycle of the LTC3675/LTC3675-1 consists of
exactly three bytes except when a clear interrupt command
is written. The first byte is always the LTC3675/LTC3675-1’s
write address. The second byte represents the sub-address.
The sub-address is a pointer which directs the subsequent
data byte within the LTC3675/LTC3675-1. The third byte
consists of the data to be written to the location pointed
to by the sub-address. The LTC3675/LTC3675-1 contain
11 control registers which can be written to.
I²C Bus Write Operation
The master initiates communication with the LTC3675/
LTC3675-1 with a START condition and the appropriate
write address. If the address matches that of the LTC3675/
LTC3675-1, the LTC3675/LTC3675-1 return an acknowl-
edge. The master should then deliver the sub-address.
Again the LTC3675/LTC3675-1 acknowledge and the cycle
is repeated for the data byte. The data byte is transferred
to an internal holding latch upon the return of its acknowl-
edge by the LTC3675/LTC3675-1. This procedure must
be repeated for each sub-address that requires new data.
After one or more cycles of [ADDRESS][SUB-ADDRESS]
[DATA], the master may terminate the communication
with a STOP condition. Multiple sub addresses may
be written to with a single address command using a
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