LTC3675_15 Datasheet, PDF (23/38 Pages) Linear Technology – 7-Channel Configurable High Power PMIC

LTC3675/LTC3675-1
Operation
Table 1. Summary of I²C Sub-Addresses and Byte Formats. Bits A7, A6, A5, A4 of Sub-Address Need to Be 0 to Access Registers
SUB-ADDRESS
OPER-
A7A6A5A4A3A2A1A0 ATION ACTION
BYTE FORMAT
D7D6D5D4D3D2D1D0
DEFAULT
D7D6D5D4D3D2D1D0 COMMENTS
0000 0000 (00h)
Write No Register
Selected
Used in the Clear Interrupt
Operation.
0000 0001 (01h)
Read/ Buck1 Register Enable, OUT_Hi-Z, Mode, Slow, DAC[3],
Write
DAC[2], DAC[1], DAC[0]
01101111
0000 0010 (02h)
Read/ Buck2 Register Enable, OUT_Hi-Z, Mode, Slow, DAC[3],
Write
DAC[2], DAC[1], DAC[0]
01101111
0000 0011 (03h)
Read/ Buck3 Register Enable, OUT_Hi-Z, Mode, Slow, DAC[3],
Write
DAC[2], DAC[1], DAC[0]
01101111
0000 0100 (04h)
Read/ Buck4 Register Enable, OUT_Hi-Z, Mode, Slow, DAC[3],
Write
DAC[2], DAC[1], DAC[0]
01101111
0000 0101 (05h)
Read/ Boost Register Enable, Unused, Mode, Slow, DAC[3],
Write
DAC[2], DAC[1], DAC[0]
00001111
0000 0110 (06h)
Read/ Buck-Boost
Write Register
Enable, Unused, Mode, Slow, DAC[3],
DAC[2], DAC[1], DAC[0]
00001111
0000 0111 (07h)
Read/ LED
Write Configuration
Register
Unused, Mode[1], Mode[0], Slow, 2XFS,
GRAD[2], GRAD[1], GRAD[0]
00001111
0000 1000 (08h)
Read/ LED DAC
Write Register
DAC[7], DAC[6], DAC[5], DAC[4], DAC[3],
DAC[2], DAC[1], DAC[0]
00000000
00000000 = LED Driver Disabled
11111111 = 25mA per String
0000 1001 (09h)
Read/ UVOT Register RESET_ALL, UV[2], UV[1], UV[0], UNUSED, 00000000
Write
UNUSED, OT[1], OT[0]
0000 1010 (0Ah)
Read/ RSTB Mask
Write Register
UNUSED, PGOOD[7], PGOOD[6], PGOOD[5], 11111111
PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]
Fault will pull RSTB low if the
corresponding bit is ‘1’
0000 1011 (0Bh)
Read/ IRQB Mask
Write Register
UNUSED, PGOOD[7], PGOOD[6], PGOOD[5], 00000000
PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]
Fault will pull IRQB low if the
corresponding bit is ‘1’
0000 1100 (0Ch)
Read Status Register UNUSED, UNUSED, PGOOD[6], PGOOD[5],
(Real Time)
PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]
Read Back
0000 1101 (0Dh)
Read Status Register UV, OT, PGOOD[6], PGOOD[5], PGOOD[4],
(Latched)
PGOOD[3], PGOOD[2], PGOOD[1]
Read Back
0000 1111 (0Fh)
Write Clear Interrupt
Clears the Interrupt Bit,
Status Latches are Unlatched
[ADDRESS][SUB-ADDRESS][DATA][SUB-ADDRESS]
[DATA] sequence. Alternatively, a REPEAT-START condition
can be initiated by the master and another chip on the I²C
bus can be addressed. This cycle can continue indefinitely
and the LTC3675/LTC3675-1 will remember the last input
of valid data that it received. Once all chips on the bus
have been addressed and sent valid data, a global STOP
can be sent and the LTC3675/LTC3675-1 will update its
command latches with the data that it had received.
interrupt. To clear an interrupt, sub address OFh must be
written, followed by sub address 00h. A complete clear
interrupt cycle would have the following write sequence:
12h, 0Fh, STOP, 12h, 00h, STOP.
I²C Bus Read Operation
The LTC3675/LTC3675-1 have eleven command registers
and two status registers. The contents of any of these
registers may be read back via I²C.
It is important to understand that until a STOP signal
is transmitted, data written to the LTC3675/LTC3675-1
command registers are not acted on by the LTC3675/
LTC3675-1. Only once a STOP signal is issued is the data
transferred to the command latch and acted on. The one
exception is when sub-address 0Fh is written to clear an
To read the data of a register, that register’s sub-address
must be provided to the LTC3675/LTC3675-1. The bus
master reads the status of the LTC3675/LTC3675-1 with
a START condition followed by the LTC3675/LTC3675-1’s
write address followed by the first data byte (the sub-
address of the register whose data needs to be read) which
36751fc
For more information www.linear.com/LTC3675
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