LTC3118_15 Datasheet, PDF (30/38 Pages) Linear Technology – 18V, 2A Buck-Boost DC/DC Converter with Low-Loss Dual Input PowerPath

LTC3118
Applications Information
Compensation Example
This section will demonstrate how to derive and select
the compensation components for a typical LTC3118 ap-
plication. Designing compensation for other applications
is a matter of substituting different values in the equations
provided based on the power stage bode plots. Since the
compensation design procedure uses a simplified model
of the LTC3118, the results from the following compensa-
tion design should always be verified with time domain
step load response tests to validate the effectiveness of
the compensation design. It is assumed that the value
and type of output capacitor will be selected based on the
guidelines provided elsewhere in this data sheet. Particular
attention needs to be paid to the voltage bias effect on
ceramic capacitors typically used for output bypassing.
Similarly, it is assumed that the inductor value and current
rating has been selected as well, based on the application
requirements.
Example Application Details:
V_IN = 3V to 15V
V_OUT = 5V
Maximum I_OUT (boost mode) = 1A, R_LOAD = 5Ω
Maximum I_OUT (buck mode) = 1A, R_LOAD = 5Ω
(could supply 2A if V_IN > 5V)
C_OUT = 100µF but use 66µF in calculations to account
for DC voltage bias effects.
L = 3.3µH
Since this application includes boost mode operation, the
first step is to calculate the worst-case RHPZ frequency
as this will dictate the maximum loop bandwidth for the
converter.
RHPZ (f)
=
V_IN2 • R_LOAD
V_OUT2 • 2π • L
=
3V² • 5Ω
5V² • 2π • 3.3µH
=
87kHz
In order to account for internal IC component variations,
it is a good practice to set the converter bandwidth, or
crossover frequency, at least 4 to 5 times lower than the
RHPZ frequency, to avoid excessive phase loss from the
RHPZ when operating in boost mode. In some instances
such as higher output voltage applications, an even greater
separation between the loop crossover frequency and
the RHPZ frequency may be necessary. In this example
design, we’ll plan to achieve a loop bandwidth (f_CC) of
20kHz, well below the RHPZ frequency. The 5V, 1A de-
sign example bode plots are shown in Figure 9. The top
curve set shows the power stage gain (and phase) in buck
(> 5V_IN) and 3V_IN boost mode operation. The DC gain in
buck mode is simply the current loop transconductance
(6A/V) multiplied by the load resistance (5Ω). The V_OUT
resistor divider will be accounted for in voltage amplifier
network.
Buck DC Gain:
20log₍6A/V•5Ω₎ = 29dB
In boost mode the gain is reduced by V_IN / V_OUT.
Boost DC Gain at 3V_IN:
20log^{⎛⎝⎜ 6A/V}
• 3V
5V
•
5Ω
⎞
⎠⎟
=
25dB
The output load pole will move depending on the output
load resistance. The power stage poles at full load are
shown in the top set of curves in Figure 9.
Output Load Pole:
1
=
1
= 480Hz
2π • R_LOAD • C_OUT 2π • 5Ω • 66µF
3118f
30
For more information www.linear.com/LTC3118