LTC3118_15 Datasheet, PDF (13/38 Pages) Linear Technology – 18V, 2A Buck-Boost DC/DC Converter with Low-Loss Dual Input PowerPath

LTC3118
Operation
If operation from V_IN1 is selected, PUMP1 connects the
low R_DSON static switch between V_IN1 and CM1 as shown.
Switch A1 is then driven on for a portion of each switching
cycle, as commanded by the PWM circuitry and powered
by the flying capacitor between BST1 and SW1. When
operating from V_IN1, PUMP2 and A2 are disabled.
Operation from V_IN2 is accomplished in a similar man-
ner, except that PUMP2 connects V_IN2 to CM2 and A2 is
commanded on by the PWM. With operation from V_IN2,
PUMP1 and A1 are disabled providing isolation from V_IN1.
PWM Mode Operation
If the MODE pin is high, or if the load current on the
converter is high enough to force PWM mode operation,
the LTC3118 operates at a fixed 1.2MHz frequency us-
ing a current mode control loop. PWM mode minimizes
output voltage ripple and yields a low noise switching
frequency spectrum. A proprietary switching algorithm
provides seamless transitions between operating modes
and eliminates discontinuities in the average inductor
current, inductor ripple current and loop transfer function
throughout all modes of operation. These advantages
result in increased efficiency, improved loop stability and
lower output voltage ripple. In PWM mode operation, both
SW1 and SW2 transition on every cycle independent of
the input and output voltages. In response to the internal
control loop command, an internal pulse width modulator
generates the appropriate switch duty cycle to maintain
regulation of the output voltage.
minimum switch low duration (typically 100ns). During the
switch low duration, switch B is turned on which forces
SW1 low and charges the flying capacitor between BST1
and SW1. This ensures that switch A1 (or A2) gate driver
power supply rail on BST1 is maintained. The duty cycle
of switch C and switch D are adjusted by the PWM circuit
to maintain output voltage regulation in boost mode.
Oscillator
The LTC3118 operates from an internal oscillator with
a nominal fixed frequency of 1.2MHz. This allows the
DC/DC converter efficiency to be maximized while still
using small external components.
Input Select Logic and V_IN Power Good Indicators
A simplified schematic diagram of the LTC3118’s input
select circuitry is shown in Figure 2. UVLO comparators
on V_IN1, V_IN2 and V_CC set minimum operating voltages to
ensure proper operation. V_CC must be greater than 2.35V
before operation is allowed from either input. Once V_CC
is valid, one of the inputs must be greater than 2V typical
before the LTC3118 enables switching. Finally, the RUN
pin voltage for the particular input must be greater than
1.22V to enable operation. This condition will be met if the
appropriate RUN pin is connected to its own V_IN, RUN1 to
V_IN1 for example, but may not be met if a resistor divider
is used to program the accurate RUN pin higher than the
V_IN UVLO minimum. Detailed discussions of V_CC, V_IN and
RUN pin UVLOs are presented in later sections.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for a minimum SW2 low duration (typically 100ns). Dur-
ing the switch low duration, switch C is turned on which
forces SW2 low and charges the flying capacitor between
BST2 and SW2. This ensures that the switch D gate driver
power supply rail on BST2 is maintained. The duty cycle of
switch A1 (or A2) and switch B are adjusted by the PWM
circuit to maintain output voltage regulation in buck mode.
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A1 (or A2)
remains on for the entire switching cycle except for the
Once the UVLO conditions are satisfied, internal V_IN1GOOD
and/or V_IN2GOOD will assert and the LTC3118 is allowed
to operate. The state of each V_INGOOD signal and the SEL
pin are decoded in logic to determine which input source
is selected, as shown on the table in Figure 2.
Open-drain indicator pins V1GD and V2GD are driven
by their respective internal V_INGOOD signals and can be
used to alert the system of undervoltage conditions on
the inputs. External pull-up resistors can be connected
between these pins and any supply voltage up to 18V.
Since these pins pull low with valid input voltages, even
in Burst Mode operation, high value resistors are recom-
mended for applications where minimal no-load quiescent
current is critical.
3118f
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