LTC3716 Datasheet, PDF (3/28 Pages) Linear Technology – 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator

LTC3716
ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 15V, V_BIAS = 5V, V_RUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
I_Q
I_RUN/SS
V_RUN/SS
V_RUN/SSLO
I_SCL
I_SDLHO
I_SENSE
DF_MAX
TG1, 2 t_r
TG1, 2 t_f
BG1, 2 t_r
BG1, 2 t_f
TG/BG t_1D
Input DC Supply Current
Normal Mode
Shutdown
Soft-Start Charge Current
RUN/SS Pin ON Threshold
RUN/SS Pin Latchoff Arming
RUN/SS Discharge Current
Shutdown Latch Disable Current
Total Sense Pins Source Current
Maximum Duty Factor
Top Gate Transition Time:
Rise Time
Fall Time
Bottom Gate Transition Time:
Rise Time
Fall Time
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
(Note 5)
V_RUN/SS = 0V
V_RUN/SS = 1.9V
V_RUN/SS Rising
V_RUN/SS Rising from 3V
Soft Short Condition V_EAIN = 0.5V, V_RUN/SS = 4.5V
V_EAIN = 0.5V
Each Channel: V_SENSE1–_{, 2} – = V_SENSE1+_{, 2}+ = 0V
In Dropout
(Note 6)
C_LOAD = 3300pF
C_LOAD = 3300pF
(Note 6)
C_LOAD = 3300pF
C_LOAD = 3300pF
C_LOAD = 3300pF Each Driver (Note 6)
1.2
mA
20
40
µA
– 0.5 –1.2
µA
1.0
1.5
1.9
V
4.1
4.5
V
0.5
2
4
µA
1.6
5
µA
– 85 – 60
µA
98
99.5
%
30
90
ns
40
90
ns
30
90
ns
20
90
ns
90
ns
BG/TG t_2D Bottom Gate Off to Top Gate On Delay C_LOAD = 3300pF Each Driver (Note 6)
Top Switch-On Delay Time
90
ns
t_ON(MIN)
Minimum On-Time
Internal V_CC Regulator
V_INTVCC
Internal V_CC Voltage
V_LDO INT INTV_CC Load Regulation
V_LDO EXT EXTV_CC Voltage Drop
V_EXTVCC
EXTV_CC Switchover Voltage
V_LDOHYS EXTV_CC Switchover Hysteresis
VID Parameters
Tested with a Square Wave (Note 7)
6V < V_IN < 30V, V_EXTVCC = 4V
I_CC = 0 to 20mA, V_EXTVCC = 4V
I_CC = 20mA, V_EXTVCC = 5V
I_CC = 20mA, EXTV_CC Ramping Positive
I_CC = 20mA, EXTV_CC Ramping Negative
180
ns
4.8
5.0
5.2
V
0.2
1.0
%
80
160
mV
q 4.5
4.7
V
0.2
V
V_BIAS
R_ATTEN
Operating Supply Voltage Range
Resistance Between ATTENIN
and ATTENOUT Pins
2.7
5.5
V
10
kΩ
ATTEN_ERR Resistive Divider Error
R_PULLUP VID0 to VID4 Pull-Up Resistance
VID_THLOW VID0 to VID4 Logic Threshold Low
VID_THHIGH VID0 to VID4 Logic Threshold High
VID_LEAK VID0 to VID4 Leakage
Oscillator and Phase-Locked Loop
(Note 8)
V_BIAS < VID0–VID4 < 7V
q – 0.25
0.25
%
40
kΩ
0.4
V
1.6
V
±1
µA
f_NOM
f_LOW
f_HIGH
R_PLLIN
I_PLLFLTR
R_RELPHS
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Resistance
Phase Detector Output Current
Sinking Capability
Sourcing Capability
Controller 2-Controller 1 Phase
V_PLLFLTR = 1.2V
V_PLLFLTR = 0V
V_PLLFLTR ≥ 2.4V
f_PLLIN < f_OSC
f_PLLIN > f_OSC
190 220 250
kHz
120 140 160
kHz
280 310 360
kHz
50
kΩ
– 15
µA
15
µA
180
Deg
3