LTC3716 Datasheet, PDF (24/28 Pages) Linear Technology – 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator

LTC3716
APPLICATIO S I FOR ATIO
[ ] ^PMAIN
=
1.2V
5.5V
(¹⁰)²
1+
(^0.005)(^110°C
−
25°C₎
0.013Ω + 1.7₍5.5V₎²₍10A₎₍300pF₎
(^300kHz) ^{= 0.45W}
The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P_SYNC
=
5.5V − 1.2V
5.5V
2₍10A₎²₍1.48₎₍0.013Ω₎
= 1.5W
A short-circuit to ground will result in a folded back current
of about:
I_SC
=
25mV
0.004Ω
+
1
2
 200ns₍5.5V₎ 


1µH


=
6.8A
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50°C junction temperature
rise is:
P_SYNC
=
5.5V − 1.2V
5.5V
(^6.8A)²(^1.48)(^0.013Ω)
= 696mW
which is less than normal, full-load conditions. Inciden-
tally, since the load no longer dissipates power in the
shorted condition, total system power dissipation is de-
creased by over 99%.
The duty factor for this application is:
DF = ^VO = ^1.2V = 0.24
V_IN 5V
Using Figure 4, the RMS ripple current will be:
I_INRMS = (20A)(0.25) = 5A_RMS
An input capacitor(s) with a 5A_RMS ripple current rating is
required.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3
along with the calculated duty factor. The output ripple in
continuous mode will be highest at the maximum input
voltage since the duty factor is < 50%. The maximum
output current ripple is:
∆I_COUT
=
V_OUT
fL
(^0.5)
at
24% D F
∆I_COUTMAX
=
1.2V
(^300kHz)(^1.0µH)
0.5
= 2A_P-P
( ) ^V_OUTRIPPLE ^{= 20mΩ 2A}_P-P ^{= 40mV}_P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3716. Check the following in your layout:
1) Are the signal and power grounds separate? The signal
ground traces should return to Pin 9 first. Connect Pin 9
to Pin 28 through a wide and straight trace. Then the signal
ground joins the power ground plane beside Pin 28. It is
recommended that the Pin 28 return to the (–) plates of
C_IN.
2) Does the LTC3716 V_OS+ pin connect to the point of
load? Does the LTC3716 V_OS– pin connect to the load
return?
PADS OF SENSE RESISTOR
TRACE TO INDUCTOR
TRACE TO OUTPUT CAP (+)
SENSE⁺ SENSE ^–
3716 F10
Figure 10. Proper Current Sense Connections
24