LTC3716 Datasheet, PDF (22/28 Pages) Linear Technology – 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator

LTC3716
APPLICATIO S I FOR ATIO
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
and output capacitance requirements over competing
solutions. Other losses including Schottky conduction
losses during dead-time and inductor core losses gener-
ally account for less than 2% total additional loss.
Transition
Loss
=
(1.7)V_IN2


I_O(MAX)
2


C_RSS
f
3) INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV_CC to
ground. The resulting dQ/dt is a current out of INTV_CC that
is typically much larger than the control circuit current. In
continuous mode, I_GATECHG = (Q_T + Q_B), where Q_T and Q_B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV_CC power through the EXTV_CC switch input
from an output-derived source will scale the V_IN current
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV_CC current results in approxi-
mately 3mA of V_IN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V_IN) to only a few percent.
4) The V_IN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the differential
amplifier output. V_IN current typically results in a small
(<0.1%) loss.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
C_IN has adequate charge storage and a very low ESR at
the switching frequency. A 50W supply will typically
require a minimum of 200µF to 300µF of output capaci-
tance having a maximum of 10mΩ to 20mΩ of ESR. The
LTC3716 2-phase architecture typically halves the input
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V_OUT shifts by an
amount equal to ∆I_LOAD(ESR), where ESR is the effective
series resistance of C_OUT(∆I_LOAD) also begins to charge or
discharge C_OUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I_TH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The I_TH external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The I_TH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <2µs will
produce output voltage and I_TH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is
better to look at the Ith pin signal which is in the feedback
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