LTC3859_15 Datasheet, PDF (29/42 Pages) Linear Technology – Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

LTC3859
APPLICATIONS INFORMATION
1000
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3859 F10
Figure 10. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f_OSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3859 can only be synchronized to an
external clock whose frequency is within range of the
LTC3859’s internal VCO, which is nominally 55kHz to 1MHz.
This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Rapid phase-locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency correspond to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase-lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 1 summarizes the different states in which the FREQ
pin can be used.
Table 1
FREQ PIN
0V
INTV_CC
Resistor to SGND
Any of the Above
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
External Clock
FREQUENCY
350kHz
535kHz
50kHz to 900kHz
Phase-Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3859 is capable of turning on the top MOSFET
(bottom MOSFET for the boost controller). It is determined
by internal timing delays and the gate charge required to
turn on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that
t_{ON(MIN)_ BUCK}
<
V_OUT
V_IN(f)
t_{ON(MIN) _}
BOOST
<
V_OUT − V_IN
V_OUT (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3859 is approximately
95ns for the bucks and 120ns for the boost. However, as
the peak sense voltage decreases the minimum on-time
gradually increases up to about 130ns. This is of particu-
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
3859fa
29