LTC3859_15 Datasheet, PDF (17/42 Pages) Linear Technology – Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

LTC3859
OPERATION
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3859’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV_CC, or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV_CC
selects 535kHz. Placing a resistor between FREQ and
SGND allows the frequency to be programmed between
50kHz and 900kHz.
A phase-locked loop (PLL) is available on the LTC3859
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3859’s phase detector adjusts the voltage (through an
internal lowpass filter) of the VCO input to align the turn-on
of controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller
2’s external top MOSFET is 180 degrees out of phase to
the rising edge of the external clock source.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop filter allows the PLL to lock in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3859’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guar-
antee over all manufacturing variations to be between
75kHz and 850kHz. In other words, the LTC3859’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Boost Controller Operation When V_IN > V_OUT
When the input voltage to the boost channel rises above
its regulated V_OUT voltage, the controller can behave
differently depending on the mode, inductor current and
V_IN voltage. In forced continuous mode, the loop works
to keep the top MOSFET on continuously once V_IN rises
above V_OUT. An internal charge pump delivers current to
the boost capacitor from the BOOST3 pin to maintain a
sufficiently high TG voltage. (The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.)
In pulse-skipping mode, if V_IN is between 100% and 110%
of the regulated V_OUT voltage, TG turns on if the inductor
current rises above a certain threshold and turns off if the
inductor current falls below this threshold. This threshold
current is set approximately to 3% of the programmed
maximum I_LIM current. If the controller is programmed to
Burst Mode operation under this same V_IN window, then
TG remains off regardless of the inductor current.
If V_IN rises above 110% of the regulated V_OUT voltage in
any mode, the controller turns on TG regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the boost channel is
asleep. With the charge pump off, there would be nothing to
prevent the boost capacitor from discharging, resulting in
an insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situation,
the chip can be switched over to forced continuous mode
to enable the charge pump, or a Schottky diode can also
be placed in parallel with the top MOSFET.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
directly from the SENSE3⁺ pin and can operate to voltages
as low as 2.5V. Since this is lower than the V_BIAS UVLO of
the chip, V_BIAS can be connected to the output of the boost
controller, as illustrated in the typical application circuit
in Figure 12. This allows the boost controller to handle
input voltage transients down to 2.5V while maintaining
output voltage regulation. If the SENSE3⁺ rises back
above 2.5V, the SS3 pin will be released initiating a new
soft-start sequence.
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