LTC3115-2_15 Datasheet, PDF (26/42 Pages) Linear Technology – 40V, 2A Synchronous Buck-Boost DC/DC Converter

LTC3115-2
Applications Information
Loop Compensation Example
This section provides an example illustrating the design of a
compensation network for a typical LTC3115-2 application
circuit. In this example a 5V regulated output voltage is
generated with the ability to supply a 500mA load from an
input power source ranging from 3.5V to 30V. To reduce
switching losses a 750kHz switching frequency has been
chosen for this example. In this application the maximum
inductor current ripple will occur at the highest input volt-
age. An inductor value of 8.2µH has been chosen to limit
the worst-case inductor current ripple to approximately
600mA. A low ESR output capacitor with a value of 20µF
is specified to yield a worst-case output voltage ripple
(occurring at the worst-case step-up ratio and maximum
load current) of approximately 12mV. In summary, the key
power stage specifications for this LTC3115-2 example
application are given below.
f = 0.75MHz, t_LOW = 0.1µs
V_IN = 3.5V to 30V
V_OUT = 5V at 500mA
C_OUT = 20µF, R_C = 10mΩ
L = 8.2µH, R_L = 45mΩ
With the power stage parameters specified, the compensa-
tion network can be designed. In most applications, the
most challenging compensation corner is boost mode
operation at the greatest step-up ratio and highest load
current since this generates the lowest frequency right half
plane zero and results in the greatest phase loss. Therefore,
a reasonable approach is to design the compensation
network at this worst-case corner and then verify that
sufficient phase margin exists across all other operating
conditions. In this example application, at V_IN = 3.5V and
the full 500mA load current, the right half plane zero will
be located at 81kHz and this will be a dominant factor in
determining the bandwidth of the control loop.
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
a phase margin of 60°, the loop crossover frequency, f_C,
should be selected as the frequency at which the phase
of the buck-boost converter reaches –180°. As a result, at
the loop crossover frequency the total phase will be simply
the 60° of phase provided by the error amplifier as shown:
Phase Margin = φ_BUCK-BOOST + φ_{ERRORAMPLIFIER} + 180°
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches –195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
crossover frequency, f_C, will be the point at which the
phase of the buck-boost converter reaches –180°. It is
generally difficult to determine this frequency analytically
given that it is significantly impacted by the Q factor of
the resonance in the power stage. As a result, it is best
determined from a Bode plot of the buck-boost converter
as shown in Figure 12. This Bode plot is for the LTC3115-2
buck-boost converter using the previously specified power
stage parameters and was generated from the small-signal
model equations using LTspice^® software. In this case,
the phase reaches –180° at 24kHz making f_C = 24kHz the
target crossover frequency for the compensated loop.
From the Bode plot of Figure 12 the gain of the power
stage at the target crossover frequency is 19dB. Therefore,
in order to make this frequency the crossover frequency
in the compensated loop, the total loop gain at f_C must
be adjusted to 0dB. To achieve this, the gain of the com-
pensation network must be designed to be –19dB at the
crossover frequency.
26
For more information www.linear.com/LTC3115-2
31152fa