LTC4012-3_15 Datasheet, PDF (24/28 Pages) Linear Technology – High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control

LTC4012-3
Applications Information
The LTC4012-3 can be soft-started with the compensation
capacitor on the ITH pin. At start-up, ITH will quickly rise
to about 0.25V, then ramp up at a rate set by the com-
pensation capacitor and the 40µA ITH bias current. The
full programmed charge current will be reached when ITH
reaches approximately 2V. With a 0.1µF capacitor, the time
to reach full charge current is usually greater than 1.5ms.
This capacitor can be increased if longer start-up times
are required, but loop bandwidth and dynamic response
will be reduced.
INTV_DD Regulator Output
Bypass the INTV_DD regulator output to GND with a low
ESR X5R or X7R ceramic capacitor with a value of 0.47µF
or larger. The capacitor used to build the BOOST supply
(C2 in Figure 11) can serve as this bypass. Do not draw
more than 30mA from this regulator for the host system,
governed by IC power dissipation.
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4012-3 package (θ_JA)
is 37°C/W, provided the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on forced air cooling and other heat
sinking means, especially the amount of copper on the
PCB to which the LTC4012-3 is attached. The following
formula may be used to estimate the maximum aver-
age power dissipation, P_D (in watts), of the LTC4012-3,
which is dependent upon the gate charge of the external
MOSFETs. This gate charge, which is a function of both
gate and drain voltage swings, is determined from speci-
fications or graphs in the manufacturer’s data sheet. For
the equation below, find the gate charge for each transistor
assuming 5V gate swing and a drain voltage swing equal
to the maximum V_CLP voltage. Maximum LTC4012-3
power dissipation under normal operating conditions is
then given by:
P_D = DCIN(3mA + I_DD + 665kHz(Q_TGATE + Q_BGATE))
– 5I_DD
where:
I_DD = Average external INTV_DD load current, if any
Q_TGATE = Gate charge of external top FET in Coulombs
Q_BGATE = Gate charge of external bottom FET in

Coulombs
PCB Layout Conciderations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4012-3 is essential.
Refer to Figure 12. For maximum efficiency, the switch
node rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4012-3 close to the switching FET gate
terminals, keeping the connecting traces short to pro-
duce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
SWITCH NODE
L1 R_SENSE
V_IN
V_BAT
C_IN
HIGH
FREQUENCY
CIRCULATING
PATH
GND
SWITCHING GROUND
C_OUT
D1
+
BAT
4012 F12
ANALOG
GROUND
SYSTEM
GROUND
Figure 12. High Speed Switching Path
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