LTC4012-3_15 Datasheet, PDF (23/28 Pages) Linear Technology – High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control

LTC4012-3
Applications Information
FET Selection
Two external power MOSFETs must be selected for use
with the charger: an N-channel power switch (top FET)
and an N-channel synchronous rectifier (bottom FET).
Peak gate-to-source drive levels are internally set to
about 5V. Consequently, logic-level FETs must be used.
In addition to the fundamental DC current, selection
criteria for these MOSFETs also include channel resis-
tance R_DS(ON), total gate charge Q_G, reverse transfer
capacitance C_RSS, maximum rated drain-source voltage
BV_DSS and switching characteristics such as t_d(ON/OFF).
Power dissipation for each external FET is given by:
( ) _PD(TOP)
=
V_BAT
• I_MAX2
• 1+
V_CLP
δ∆T
R_DS(ON)
+ k • V_CLP2 • I_MAX • C_RSS • 665kHz
( ) ( ) _{PD(BOT) =}
V_CLP – V_BAT
• I_MAX2 •
V_CLP
1+ δ∆T R_DS(ON)
where δ is the temperature dependency of R_DS(ON),
ΔT is the temperature rise above the point specified in
the FET data sheet for R_DS(ON) and k is a constant in-
versely related to the internal LTC4012-3 top gate driver.
The term (1 + δ ΔT) is generally given for a MOSFET in the
form of a normalized R_DS(ON) curve versus temperature,
but δ of 0.005/°C can be used as a suitable approxima-
tion for logic-level FETs if other data is not available.
C_RSS = ΔQ_GD/ΔV_DS is usually specified in the MOSFET
characteristics. The constant k = 2 can be used in esti-
mating top FET dissipation. The LTC4012-3 is designed
to work best with external FET switches with a total gate
charge at 5V of 15nC or less.
For V_CLP < 20V, high charge current efficiency generally
improves with larger FETs, while for V_CLP > 20V, top gate
transition losses increase rapidly to the point that using
a topside NFET with higher R_DS(ON) but lower C_RSS can
actually provide higher efficiency. If the charger will be
operated with a duty cycle above 85%, overall efficiency
is normally improved by using a larger top FET.
The synchronous (bottom) FET losses are greatest at high
input voltage or during a short circuit, which forces a low
side duty cycle of nearly 100%. Increasing the size of this
FET lowers its losses but increases power dissipation in the
LTC4012-3. Using asymmetrical FETs will normally achieve
cost savings while allowing optimum efficiency.
Select FETs with BV_DSS that exceeds the maximum V_CLP
voltage that will occur. Both FETs are subjected to this level
of stress during operation. Many logic-level MOSFETs are
limited to 30V or less.
The LTC4012-3 uses an improved adaptive TGATE and
BGATE drive that is insensitive to MOSFET inertial delays,
t_d(ON/OFF), to avoid overlap conduction losses. Switching
characteristics from power MOSFET data sheets apply
only to a specific test fixture, so there is no substitute for
bench evaluation of external FETs in the target application.
In general, MOSFETs with lower inertial delays will yield
higher efficiency.
Diode Selection
A Schottky diode in parallel with the bottom FET and/or
top FET in an LTC4012-3 application clamps SW during
the non-overlap times between conduction of the top and
bottom FET switches. This prevents the body diode of the
MOSFETs from forward biasing and storing charge, which
could reduce efficiency as much as 1%. One or both diodes
can be omitted if the efficiency loss can be tolerated. A 1A
Schottky is generally a good size for 3A chargers due to the
low duty cycle of the non-overlap times. Larger diodes can
actually result in additional efficiency (transition) losses
due to larger junction capacitance.
Loop Compensation and Soft-Start
The three separate PWM control loops of the LTC4012-3
can be compensated by a single set of components at-
tached between the ITH pin and GND. As shown in the
typical LTC4012-3 application, a 6.04k resistor in series
with a capacitor of at least 0.1µF provides adequate loop
compensation for the majority of applications.
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